High-Speed Analog Layout Engineer

3Core Systems, Inc

. Design physical silicon layouts for high-frequency or high-speed mixed-signal circuits, including SerDes, ADCs, DACs, PLLs, and high-speed blocks .

Posted 11/12/2026contractRemote • Texas • United StatesMid-LevelSeniorWebsite

Core Competencies

Role fit

Core Competencies

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Expertise in designing physical silicon layouts for high-frequency mixed-signal circuits, with a strong focus on advanced CMOS/FinFET nodes and proficiency in DRC, LVS, and ESD protection. Demonstrated ability in hierarchical block integration and addressing layout-dependent effects.

Highest-signal resume keywords

TSMC 4NM ExperienceCustom IC Layout ExperienceHigh-Frequency Mixed-Signal Circuit DesignHierarchical Block IntegrationDRC, LVS, ERC Closure

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Physical Silicon Layout DesignHigh-Speed Circuit DesignMicro-Bump Co-DesignDevice MatchingCommon-Centroid StructuresGuard RingsIsolation TechniquesShielding TechniquesLayout-Dependent EffectsAdvanced CMOS/FinFET Nodes

Industry Keywords

SerDesADCsDACsPLLsEM/IR ReliabilityESD ProtectionFloor PlanningChip-Top-Level Floor PlansAntenna RulesDeep Sub-Micron

About the role

Key responsibilities & impact

Design physical silicon layouts for high-frequency or high-speed mixed-signal circuits, including SerDes, ADCs, DACs, PLLs, and high-speed blocks
Create block-level and chip-top-level floor plans
Manage hierarchical block integration
Handle micro-bump or package-aware co-design
Address layout-dependent effects, device matching, common-centroid structures, guard rings, isolation, and shielding
Ensure closure on DRC, LVS, ERC, antenna rules, EM/IR reliability, and ESD protection

Requirements

What you’ll need

Must have TSMC 4NM experience
Generally 5 to 12+ years of hands-on custom IC layout experience
Experience in deep sub-micron or advanced CMOS/FinFET nodes
Experience with advanced nodes such as TSMC N3, N5, or N7
Experience at lower nodes (N3, N5) is critical
Experience designing physical silicon layout for high-frequency or high-speed mixed-signal circuits
Knowledge of floor planning and hierarchical block integration
Experience with micro-bump or package-aware co-design
Knowledge of layout-dependent effects (LOD, WPE, LDE)
Expertise in device matching and common-centroid structures
Experience with guard rings, isolation, and shielding, including coaxial, differential, and ground shields
Experience closing DRC, LVS, ERC, antenna rules, EM/IR reliability, and ESD protection

Benefits

Comp & perks

Contract engagement for 6–12 months