Design Engineer

AccelerComm Ltd

. Work on non-terrestrial communications technology, including a 5G base station deployed on satellites .

Posted 9/17/2026full-timeSouthampton • United KingdomMid-LevelSeniorWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in RTL design using Verilog or SystemVerilog for ASIC and FPGA products, with a strong focus on digital design, signal processing algorithms, and hardware optimization techniques. Proficient in collaborating across teams to deliver integrated solutions while adhering to engineering methodologies and project management practices.

Highest-signal resume keywords

RTL Design Using Verilog/SystemVerilogDigital Design for ASIC/FPGASignal Processing AlgorithmsEDA Tools for Simulation and SynthesisPower Management Techniques

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

RTL Language (Verilog, SystemVerilog)Digital DesignSignal Processing AlgorithmsPower Management TechniquesTiming AnalysisC++/SystemCScripting Language (Python)High-Speed Interfaces (PCI-E, JESD)UVM Verification TechniquesAMBA Bus Protocols

Soft Skills

CollaborationTechnical Documentation Writing

Tools & Technologies

EDA ToolsFPGA Design ToolsASIC Backend Tools

Industry Keywords

Non-Terrestrial Communications5G Base StationBaseband Signal ProcessingHardware AccelerationMicro-ArchitectureTestbenchesEngineering MethodologiesAgile MethodologyWaterfall MethodologyRequirement Capture

Tech Stack

Tools & technologies

PythonC++

About the role

Key responsibilities & impact

Work on non-terrestrial communications technology, including a 5G base station deployed on satellites
Develop baseband signal-processing technology using hardware acceleration for error resilience, capacity, and power efficiency
Work on space-qualified devices, delivering standalone IP and integrated IP solutions
Work with senior hardware team members to understand requirements and hardware architectures and translate them into RTL micro-architectures
Implement designs targeting FPGA and ASIC using industry-standard techniques
Create appropriate testbenches
Support verification of implementations and fix identified issues
Follow and improve engineering methodologies, processes, and design techniques
Collaborate across micro-architecture, design, verification, physical implementation, and optimisation for ASIC and FPGA

Requirements

What you’ll need

Knowledge of an RTL language (Verilog, SystemVerilog) for complex ASIC/FPGA products
Strong skillset in delivering digital designs in the ASIC or FPGA industry
Track record in collaborating across teams to produce integrated solutions
Experience writing technical documentation, including design specifications, user guides, and verification plans
Experience using EDA tools for simulation and synthesis
Knowledge of timing and hardware-resource optimisation for high-throughput data or signal-processing applications
Experience with power-management techniques, synthesis, and timing analysis
Knowledge of communications signal-processing algorithms, such as error correction, equalisation, channel estimation, and beamforming
Familiarity with AMBA bus protocols
Understanding of UVM verification techniques or practical experience using UVM for IP verification
Experience using C++/SystemC for design modelling and integration
Experience with high-speed interfaces such as PCI-E or JESD
Knowledge of a scripting language such as Python
Knowledge of project methodologies across the design lifecycle, including agile and waterfall, requirement capture, and traceability
Experience with AMD FPGAs and associated design tools or EDA ASIC backend tools

Benefits

Comp & perks

Competitive salaries depending on skills and experience
Bonus scheme paying up to 20% of salary annually, depending on performance
EMI share options issued periodically
Pension
Private health insurance
Coffee shop at Southampton Science Park offices
Bike storage
Showers
Free parking
EV charging points
Flexible working hours
Hybrid working