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Design Engineer
AccelerComm Ltd. Work closely with senior hardware team members to understand requirements and hardware architectures and translate them into micro-architectures for RTL implementations .
Core Competencies
Role fitCore Competencies
Use this summary to align your resume positioning with the role.
Demonstrates expertise in RTL design using Verilog and SystemVerilog for ASIC and FPGA implementations, with a strong focus on digital design, verification, and optimization techniques. Proficient in collaborating across teams to deliver integrated solutions for satellite-based 5G communications.
Highest-signal resume keywords
RTL Design Using VerilogDigital Design in ASIC/FPGAUVM Verification TechniquesEDA Tools for Simulation and SynthesisCommunications Signal-Processing Algorithms
ATS Keywords
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Hard Skills
VerilogSystemVerilogC++SystemCPythonTiming AnalysisPower-Management TechniquesHigh-Speed InterfacesAMBA Bus ProtocolsSignal-Processing Algorithms
Soft Skills
CollaborationTechnical Documentation
Tools & Technologies
EDA ToolsFPGA Design ToolsASIC Backend Tools
Industry Keywords
ASICFPGA5G CommunicationsSatellite TechnologyDesign Methodologies
Tech Stack
Tools & technologiesPythonC++
About the role
Key responsibilities & impact- Work closely with senior hardware team members to understand requirements and hardware architectures and translate them into micro-architectures for RTL implementations
- Implement designs targeting FPGA and ASIC using industry-standard techniques, including creating appropriate testbenches
- Support verification of implementations and fix issues found
- Engage with and adhere to AccelerComm engineering methodology, processes, and design techniques
- Improve efficiency and quality of the design flow and final product
- Collaborate across the design flow, including micro-architecture, design, verification, physical implementation, and optimization for ASIC and FPGA
- Work on space-qualified devices delivering standalone IP and integrated IP solutions
- Contribute to technology for satellite-based 5G communications and global mobile coverage
Requirements
What you’ll need- Knowledge of an RTL language (Verilog, SystemVerilog) for complex ASIC/FPGA products
- Strong skillset delivering digital designs in the ASIC or FPGA industry
- Track record collaborating across teams to produce integrated solutions
- Experience writing technical documentation, including design specifications, user guides, and verification plans
- Experience using EDA tools for simulation and synthesis
- Knowledge of timing and hardware-resource optimization for high-throughput data or signal-processing applications
- Experience with power-management techniques, synthesis, and timing analysis
- Knowledge of communications signal-processing algorithms, such as error correction, equalisation, channel estimation, and beamforming
- Familiarity with AMBA bus protocols
- Understanding of UVM verification techniques or practical experience using UVM for IP verification
- Experience using C++/SystemC for design modelling and integration
- Experience with high-speed interfaces such as PCI-E or JESD
- Knowledge of a scripting language such as Python
- Knowledge of project methodologies across the design lifecycle, including agile and waterfall, requirement capture, and traceability
- Experience with AMD FPGAs and associated design tools or EDA ASIC backend tools
Benefits
Comp & perks- Bonus scheme paying up to 20% of salary annually, depending on performance
- EMI share options issued periodically
- Pension
- Private health insurance
- Coffee shop at Southampton Science Park offices
- Bike storage
- Showers
- Plenty of free parking
- EV charging points