Senior Design Engineer

AccelerComm Ltd

. Work with Algorithm and System Architecture teams to understand requirements and translate them into micro-architectures for RTL implementations .

Posted 9/17/2026full-timeCambridge • United KingdomSeniorWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expert knowledge of RTL languages such as Verilog and SystemVerilog for ASIC and FPGA designs, with a strong focus on optimizing timing and hardware resources. Proficient in collaborating across teams to deliver integrated solutions and produce comprehensive technical documentation.

Highest-signal resume keywords

RTL Language Expertise (Verilog, SystemVerilog)Digital Design Delivery in ASIC and FPGAEDA Tools for Simulation and SynthesisPower Management Techniques and Timing AnalysisUVM Verification Techniques

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Applicant Tracking System Keywords

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Hard Skills

RTL Language (Verilog, SystemVerilog)Digital DesignTiming OptimizationPower Management TechniquesTechnical Documentation WritingC++/SystemC for Design ModellingHigh-Speed Interfaces (PCI-E, JESD)Scripting Language (Python)Communications Signal-Processing AlgorithmsAMBA Bus Protocols

Soft Skills

Collaboration Across TeamsProblem-Solving

Tools & Technologies

EDA ToolsFPGA Development PlatformsASIC Backend Tools

Industry Keywords

Micro-ArchitectureDesign VerificationDesign Flow EfficiencySatellite-Based CommunicationsNon-Terrestrial Communications

Tech Stack

Tools & technologies

PythonC++

About the role

Key responsibilities & impact

Work with Algorithm and System Architecture teams to understand requirements and translate them into micro-architectures for RTL implementations
Implement designs targeting FPGA and ASIC using industry-standard techniques, including appropriate testbenches
Deploy designs onto FPGA development platforms for validation and system integration
Follow and improve AccelerComm engineering methodologies, processes, and design techniques to improve design-flow efficiency and product quality
Collaborate across the design flow, including micro-architecture, design, verification, physical implementation, and optimization for ASIC and FPGA
Work on space-qualified devices delivering standalone IP and integrated IP solutions for satellite-based non-terrestrial communications

Requirements

What you’ll need

Expert knowledge of an RTL language (Verilog, SystemVerilog) for complex ASIC/FPGA products
Strong skillset in delivering digital designs in the ASIC and FPGA industry
Experience optimizing timing and hardware resources for high-throughput data or signal-processing applications
Experience with power management techniques, synthesis, and timing analysis
Track record collaborating across teams to produce integrated solutions
Experience writing technical documentation, including design specifications, user guides, and verification plans
Expert user of EDA tools for simulation and synthesis
Knowledge of communications signal-processing algorithms such as error correction, equalisation, channel estimation, and beamforming is desirable
Familiarity with AMBA bus protocols is desirable
Understanding of UVM verification techniques or practical UVM experience for IP verification is desirable
Experience using C++/SystemC for design modelling and integration is desirable
Experience with high-speed interfaces such as PCI-E or JESD is desirable
Knowledge of a scripting language such as Python is desirable
Knowledge of project methodologies across the design lifecycle, including agile and waterfall, requirement capture, and traceability is desirable
Experience with AMD FPGAs and associated design tools or EDA ASIC backend tools is desirable

Benefits

Comp & perks

Competitive salaries depending on skills and experience
Bonus scheme paying up to 20% of salary annually, depending on performance
EMI share options issued periodically
Pension
Private health insurance
Flexible working hours
Hybrid working