Senior Verification Engineer

AccelerComm Ltd

. Verify RTL implementations for advanced wireless communications IP and modem subsystems .

Posted 10/14/2026full-timeUnited StatesSeniorWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in verifying RTL implementations for advanced wireless communications, with strong skills in SystemVerilog and UVM. Proficient in developing verification plans, testbenches, and automation workflows while mentoring junior colleagues.

Highest-signal resume keywords

SystemVerilogUVMRTL Design PrinciplesDigital ASIC VerificationFPGA Verification

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Verification PlansTestbenchesAssertionsScoreboardsCoverage ModelsDirected VerificationConstrained-Random VerificationDebugging RTL IssuesCoverage-Driven VerificationAssertion-Based Verification

Soft Skills

MentoringCollaboration

Tools & Technologies

LinuxPythonTclBashCI Workflows

Industry Keywords

Wireless CommunicationsFPGA DeploymentASIC Tape-OutIntegration ActivitiesDesign Reviews

Tech Stack

Tools & technologies

LinuxPython

About the role

Key responsibilities & impact

Verify RTL implementations for advanced wireless communications IP and modem subsystems
Ensure designs meet functional, performance and quality requirements before FPGA deployment and ASIC tape-out
Develop verification plans from design and architecture specifications
Create and maintain SystemVerilog/UVM verification environments
Develop testbenches, assertions, scoreboards and coverage models
Execute directed and constrained-random verification
Analyse coverage and debug RTL and verification issues
Support subsystem and system-level integration activities
Contribute to automation, regression and CI workflows
Participate in design reviews and verification sign-off
Mentor and support junior colleagues

Requirements

What you’ll need

Degree in Electronic Engineering, Computer Engineering or a related discipline
At least 3 years experience verifying digital ASIC and/or FPGA designs
Strong SystemVerilog and UVM skills
Understanding of RTL design principles and hardware implementation
Experience with coverage-driven and assertion-based verification
Linux proficiency and scripting skills (Python, Tcl or Bash)
Experience using AI to accelerate verification without sacrificing quality
Ability to work across multiple teams
Applicants must have existing H-1B visa or practical training work authorization if seeking a change of employer; new applications cannot be sponsored

Benefits

Comp & perks

Bonus scheme paying up to 20% of salary annually, depending on performance
Stock options
401K
Health, dental and optical insurance
Flexible working hours
Hybrid working
Existing H-1B visa or practical training work authorization applicants welcome to apply when seeking a change of employer