Associate Design Verification Engineer

Analog Devices

. Contribute to verification of digital, analog, and mixed-signal integrated circuits prior to tape-out .

Posted 10/7/2026full-timeUnited StatesJuniorMid-LevelWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in SystemVerilog for digital verification, including test bench development and simulation-based verification. Proficient in analyzing and verifying digital hardware designs while collaborating effectively with cross-functional teams.

Highest-signal resume keywords

SystemVerilog ProficiencyDigital Verification ConceptsTest Bench DevelopmentAutomation Scripting (Python, Perl, Tcl)Coverage-Driven Verification

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Digital Design VerificationRTL Design PrinciplesSimulation AnalysisDebugging Technical IssuesConstrained-Random Test Case DevelopmentFunctional Coverage AnalysisMixed-Signal SimulationBehavioral ModelingUVM ExposureSystemVerilog Assertions (SVA)

Soft Skills

Strong Communication SkillsTeam Collaboration

Tools & Technologies

EDA Simulation ToolsDebugging Tools

Industry Keywords

Semiconductor SolutionsStandard Communication Protocols (I2C, SPI, UART)Export Control Compliance

Tech Stack

Tools & technologies

PerlPython

About the role

Key responsibilities & impact

Contribute to verification of digital, analog, and mixed-signal integrated circuits prior to tape-out
Develop and execute test benches using SystemVerilog and established verification methodologies
Create and maintain functional and coverage-driven verification environments
Develop directed and constrained-random test cases to validate design functionality and performance
Perform code and functional coverage analysis
Debug simulation failures, analyze verification results, and identify potential design issues
Collaborate with design engineers to understand requirements and verify implementation accuracy
Support verification planning, documentation, and design review activities
Use scripting and automation to improve verification efficiency and productivity
Contribute to mixed-signal simulation and behavioral modeling activities where applicable
Collaborate with cross-functional engineering teams to deliver high-quality semiconductor solutions
Required travel: 10% of the time

Requirements

What you’ll need

Knowledge of SystemVerilog and digital verification concepts, including test bench development and simulation-based verification
Understanding of RTL design principles and ability to analyze and verify digital hardware designs
Familiarity with coverage-driven verification concepts and structured verification practices
Experience or coursework using Python, Perl, or Tcl for automation and productivity improvements
Understanding of standard communication protocols such as I2C, SPI, UART, or similar interfaces
Ability to analyze simulation results, investigate failures, and resolve technical issues
Strong written and verbal communication skills and ability to work effectively in a team environment
Bachelor's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, or a related field (preferred)
0–2 years of experience in digital design verification or a related engineering discipline
New graduates with relevant academic projects, internships, or coursework in digital design, verification, or semiconductor engineering are encouraged to apply
Exposure to UVM, constrained-random verification, or SystemVerilog Assertions (SVA) is a plus
Familiarity with EDA simulation and debugging tools is preferred
Exposure to mixed-signal simulation, analog behavioral modeling, or object-oriented programming concepts is beneficial
Applicants may be subject to export licensing review; certain technical-data access may require eligibility under U.S. export-control rules

Benefits

Comp & perks

Beneficial employee programs
Continuous learning opportunities
Sustainable future-focused workplace practices