Principal Digital Design Engineer

Analog Devices

. Provide technical leadership and expertise to digital design engineers across digital design and quality assurance .

Posted 10/22/2026full-timeBangalore • IndiaLeadWebsite

Core Competencies

Role fit

Core Competencies

Use this summary to align your resume positioning with the role.

Demonstrates expertise in digital design and architecture, particularly in Verilog and SystemVerilog, with a strong focus on ASIC/SoC product development and design verification. Capable of leading large teams, managing complex hardware projects, and ensuring adherence to quality metrics and design processes.

Highest-signal resume keywords

Verilog/SystemVerilog CodingASIC/SoC Product DevelopmentDesign Verification RequirementsDigital Design ConceptsProject Management

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

RTL CodingTiming ConstraintsStatic Timing AnalysisLow-Power DesignDesign Quality AssuranceDigital IP PackagingBenchmarking FlowsPower AnalysisFormal EquivalenceDFT Concepts

Soft Skills

Interpersonal SkillsTeamworkCommunication SkillsMentoring

Tools & Technologies

MethodicsPerforceGitHubDigital IP Catalog

Certifications & Qualifications

B.E. / B. Tech Degree in Electrical/Electronics/Computer Science

Industry Keywords

ASICSoCDesign VerificationControl-PathData-PathProtocolsDDRPCIeMIPIDSP Fundamentals

About the role

Key responsibilities & impact

Provide technical leadership and expertise to digital design engineers across digital design and quality assurance
Architect and design configurable digital blocks, including accelerators and datapath IP, using Verilog/SystemVerilog
Define Power/Performance/Area tradeoffs through built-in configurability
Understand and integrate heterogeneous processor cores and subsystems
Align team schedules, milestones, commitments, and deliverables with stakeholders
Conduct detailed design reviews and drive adherence to quality metrics
Create and manage collaborative, efficient design-team workflows
Establish project visibility systems and design-review processes
Drive Design Management and IP-centric infrastructure and flows across Methodics, Perforce, GitHub, and IP catalogs
Develop and maintain a digital IP catalog for business-unit customers
Build expertise in complex interfaces, peripherals, and protocols including DDR, Ethernet, eMMC/SD, MIPI, DisplayPort, HDMI, PCIe, and high-speed D2D
Package digital IP for integration into design flows, including RTL, constraints, CDC waivers, timing waivers, DFT DRCs and waivers, and software programming sequences
Evaluate third-party IP on PPA, design quality, DFT, DV robustness, integration ease, and other qualitative aspects
Establish consistent benchmarking flows for home-grown and third-party IP
Consolidate and curate digital IP blocks, processor cores, peripherals, protocol IP, and related collateral
Provide clear, actionable recommendations and remove complexity and ambiguity from team processes
Serve as communications focal point, compile stakeholder status updates, and escalate critical issues and risks

Requirements

What you’ll need

Minimum B.E. / B. Tech degree in Electrical/Electronics/Computer Science
15+ years of relevant experience focused on definition, architecture, microarchitecture, design, and hands-on RTL coding using Verilog and SystemVerilog
Strong understanding of ASIC/SoC product development, including Design Verification, timing constraints/closure, physical implementation, and quality assurance flows
Prior experience in several ASIC/SoC development aspects
Experience managing or handling large complex hardware projects in a lead role
Strong understanding of control-path and data-path digital design concepts
Experience specifying Design Verification requirements, including test plans and coverage metrics, and evaluating DV quality
Strong knowledge of Lint, CDC, formal equivalence, DFT concepts, power analysis, and low-power design
Experience developing timing constraints and carrying out logic synthesis and static timing analysis
Ability to technically mentor a large digital design team
Good interpersonal, teamwork, and communication skills
Strong understanding of APB, AHB, AXI, and Stream protocols
Knowledge of processor/SoC architecture and/or DSP fundamentals
Ability to serve as communications focal point, compile regular status updates, and escalate critical issues and risks
Applicants may be required to undergo export licensing review unless they are U.S. citizens, U.S. permanent residents, or protected individuals
Willingness to travel 10% of the time
Ability to work 1st Shift/Days

Benefits

Comp & perks

Equal opportunity employment
Required travel: 10% of the time