Principal Engineer, Analog Design Engineering

Analog Devices

. Lead development of analog/mixed-signal IC products from architecture exploration through transistor-level implementation and verification .

Posted 10/12/2026full-timeTaipei • TaiwanLeadWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in analog and mixed-signal IC design, including power management solutions such as switching regulators and LDOs. Proven ability to lead cross-functional teams in the development and validation of complex systems while applying advanced design methodologies and AI tools.

Highest-signal resume keywords

Analog/Mixed-Signal IC DesignPower Management IC DevelopmentCadence Design EnvironmentSimplis ProficiencyTechnical Leadership

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Analog Circuit DesignMixed-Signal SimulationTransistor-Level ImplementationDC-DC Switching Regulator DesignFeedback/Control Loop DesignSystem Architecture DefinitionSilicon DebugLayout TechniquesVerification MethodologiesAI Tools Application

Soft Skills

MentoringCollaborationCross-Functional Team Leadership

Tools & Technologies

Verilog-AVerilog-AMSPCB Design/LayoutLab EvaluationProduction Test

Certifications & Qualifications

MSEE or Ph.D. in Electrical Engineering

Industry Keywords

Mixed-Signal SystemsSoC EnvironmentsSemiconductor Device PhysicsAnalog Building BlocksExport Licensing

Tech Stack

Tools & technologies

Switching

About the role

Key responsibilities & impact

Lead development of analog/mixed-signal IC products from architecture exploration through transistor-level implementation and verification
Determine technical feasibility and develop business cases for new product concepts through customer engagements
Collaborate with local and global design, test, applications, and marketing engineers to define systems and analog-block specifications
Integrate blocks into larger mixed-signal systems
Provide technical oversight for IC layout, packaging, PCB design/layout, lab evaluation, and production test
Mentor engineers and provide technical leadership
Apply AI tools and techniques to design automation, optimization, and modeling workflows
Improve analog design and verification methodologies to reduce time and cost to market
Architect, design, and validate switching regulators, LDOs, charge pumps, and switched-capacitor converter architectures
Model DC-DC switching regulator behavior with Simplis, Verilog-A, or Verilog-AMS
Develop closed-loop control architectures, compensation strategies, loop-stability optimization, and transient-response enhancements
Define end-to-end power architectures with system architects for mixed-signal SoCs
Lead power-block bring-up, silicon debug, and optimization across process, voltage, and temperature variations

Requirements

What you’ll need

MSEE or Ph.D. EE degree
Minimum 12 years’ experience as an analog/mixed-signal IC designer
Expert-level knowledge of analog and mixed-signal circuit design and layout techniques, tools, flows, and semiconductor device physics
Extensive hands-on experience in power management IC development, including switching regulators, LDOs, charge pumps, and feedback/control loop design
Understanding of analog circuit design fundamentals, including amplifiers, ADCs/DACs, PLL, bandgap references, biasing circuits, and related analog building blocks
Proficiency in Cadence design environment and mixed-signal simulation
Proficiency in Simplis
Ability to work effectively across geographically distributed and cross-functional teams
Ability to independently lead circuit-block or complete-system design and development from architecture through silicon validation and product debug
Experience integrating power management and analog IP into complex SoC environments is a strong advantage
Knowledge of Verilog hardware description language is a plus
Experience or awareness of AI-assisted tools is a plus
Applicants may be subject to U.S. export licensing review, except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3)

Benefits

Comp & perks

Equal opportunity employer
No required travel
1st shift/days schedule