Staff Engineer – DFT Engineering

Analog Devices

. Collaborate with Design, Architecture, PTE, and Physical Design teams to ensure testability of complex integrated circuits .

Posted 9/18/2026full-timeBangalore • IndiaLeadWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates extensive expertise in DFT methodologies, including scan chains, ATPG, and MBIST, while effectively collaborating with cross-functional teams to optimize testability of integrated circuits. Proficient in using Siemens and Cadence EDA tools for DFT analysis and automation scripting in Perl, Tcl, or Python.

Highest-signal resume keywords

DFT MethodologiesSiemens DFT ToolsATPG Test PatternsDigital Design FundamentalsProblem-Solving Skills

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

DFT DesignScan CompressionMBIST DesignATPG GenerationDFT DRC ChecksBoundary ScanLow-Power DFT TechniquesRTL CodingLint/CDCDFT Verification Plans

Soft Skills

Team CollaborationCommunication SkillsInterpersonal SkillsMentorship

Tools & Technologies

Siemens EDA ToolsCadence DFT ToolsPerlTclPython

Industry Keywords

Integrated CircuitsTestability OptimizationAnalog DFTJTAG ArchitectureDFT STA Constraint Development

Tech Stack

Tools & technologies

PerlPython

About the role

Key responsibilities & impact

Collaborate with Design, Architecture, PTE, and Physical Design teams to ensure testability of complex integrated circuits
Design and implement DFT features including scan chains, compression, and built-in self-test structures
Conduct DFT DRC checks in RTL/netlist databases
Use Siemens DFT tools for DFT analysis and testability optimization
Generate manufacturing ATPG test patterns for stuck-at and transition fault models using on-chip test compression
Design and verify MBIST, including repair, using Siemens EDA tools
Validate DFT structures and patterns in RTL and netlist with and without SDF
Define and implement DFT verification plans with the verification team
Coordinate with physical design on DFT implementation and constraint strategies for synthesis/STA
Analyze and debug test failures with the test engineering team
Provide guidance and mentorship to junior DFT engineers

Requirements

What you’ll need

Bachelor's/Master's degree in Electrical/Electronic Engineering, or a related field
7–10 years of hands-on experience in DFT methodologies and techniques
Strong knowledge of LBIST, ATPG, DFT DRC, scan compression, low-power DFT techniques, MBIST, boundary scan, analog DFT, JTAG architecture, and DFT STA constraint development
Hands-on experience/expertise in Cadence/Siemens DFT EDA tools for scan stitching, DRC, ATPG, coverage improvement, MBIST, and boundary scan
Proficiency in Perl, Tcl, and/or Python for automation
Solid understanding of digital design fundamentals, RTL coding, Lint/CDC, low-power checks, and ASIC design flow
Excellent problem-solving skills and ability to work effectively in a team-oriented environment
Strong communication and interpersonal skills
Applicants may be subject to export licensing review unless they are US Citizens, US Permanent Residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3)

Benefits

Comp & perks

Required travel: 10% of the time