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Senior Module Engineer, Hybrid Bonding
Applied Materials. Develop and optimize die-to-wafer hybrid bonding processes for advanced packaging applications .
Posted 9/17/2026full-timeSanta Clara • California • United StatesSenior💰 $147,000 - $202,500 per yearWebsite
Core Competencies
Role fitCore Competencies
Use this summary to align your resume positioning with the role.
Demonstrates expertise in hybrid bonding processes, semiconductor process development, and advanced packaging technologies. Proficient in statistical process control, failure analysis, and cross-functional project leadership.
Highest-signal resume keywords
Hybrid BondingCu-Cu Interconnect FormationStatistical Process ControlDOE MethodologiesFailure Analysis
ATS Keywords
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Hard Skills
Semiconductor Process DevelopmentSurface ChemistryPlasma ActivationDefect EngineeringMetrology TechniquesThermocompression BondingWafer BondingAdvanced PackagingChiplet IntegrationElectrical Test Structures
Soft Skills
MentoringCollaborationPresentation Skills
Tools & Technologies
JMPMinitabCSAMX-ray InspectionFIB/SEMAFMOptical Metrology
Industry Keywords
Materials ScienceElectrical EngineeringMechanical EngineeringChemical EngineeringPhysicsSemiconductor ManufacturingHBM Development3D Stacking Technologies200 mm Wafer Manufacturing300 mm Wafer Manufacturing
Tech Stack
Tools & technologiesRay
About the role
Key responsibilities & impact- Develop and optimize die-to-wafer hybrid bonding processes for advanced packaging applications
- Establish process windows for surface preparation, plasma activation, die placement, alignment and overlay control, bonding temperature and pressure, and post-bond annealing
- Drive Cu-Cu and dielectric-dielectric interconnect formation for electrical performance and reliability
- Support integration into memory architectures, chiplet-based systems, silicon interposers, system-on-wafer platforms, and co-packaged optics
- Resolve process interactions and yield excursions with integration teams
- Identify root causes of bond voids, die shift, overlay errors, non-uniform bonding, and particle contamination
- Use DOE methodologies and statistical process control to improve yield and robustness
- Characterize bonding quality using CSAM, X-ray inspection, FIB/SEM, AFM, optical metrology, and electrical test structures
- Develop correlations between process parameters and package performance
- Collaborate with equipment engineering teams on hybrid bonding systems, die placement tools, plasma activation modules, surface preparation modules, and integrated process control solutions
- Evaluate and qualify next-generation bonding platforms
- Define and execute reliability tests including thermal cycling, HTOL, mechanical pull/shear testing, and moisture sensitivity evaluations
- Drive failure analysis and corrective actions
- Lead cross-functional projects from concept through technology transfer
- Publish technical results internally and externally
- Present development progress to engineering leadership and customers
- Mentor junior engineers and researchers
Requirements
What you’ll need- M.S. in Materials Science, Electrical Engineering, Mechanical Engineering, Chemical Engineering, Physics, or Semiconductor Manufacturing, or Ph.D. in one of these disciplines
- Minimum 5+ years of semiconductor process development experience after graduate degree
- Direct experience in hybrid bonding, thermocompression bonding, wafer bonding, advanced packaging, HBM development, Cu interconnect technology, or chiplet integration
- Strong understanding of Cu-Cu interconnect formation, surface chemistry and plasma activation, CMP and planarization, defect engineering, semiconductor process integration, and statistical process analysis
- Experience with DOE and JMP/Minitab analysis tools
- Familiarity with metrology and failure analysis techniques
- Preferred: Ph.D. with 5+ years industry experience
- Preferred experience in HBM or 3D stacking technologies, hybrid bonding equipment development, DBI, die placement systems, advanced packaging process integration, AI/HPC packaging architectures, and 200 mm/300 mm wafer manufacturing environments
- Track record of patents, publications, or conference presentations preferred
- Willingness to travel 10% of the time
Benefits
Comp & perks- Comprehensive benefits package
- Bonus program eligibility, as applicable
- Stock award program eligibility, as applicable
- Relocation eligibility
- Supportive work culture encouraging learning, development, and career growth
- Personal and professional growth and wellbeing programs and support
- 10% travel