Analog Layout Engineer

Arrow Electronics

. Design physical silicon layouts for high-frequency or high-speed mixed-signal circuits, including SerDes, ADCs, DACs, PLLs, and high-speed blocks .

Posted 10/24/2026full-timeAustin • Texas • United StatesMid-LevelSeniorWebsite

Core Competencies

Role fit

Core Competencies

Use this summary to align your resume positioning with the role.

Expertise in designing physical silicon layouts for high-frequency mixed-signal circuits, with a strong focus on advanced CMOS/FinFET nodes and layout-dependent effects. Proficient in hierarchical block integration, ensuring compliance with DRC, LVS, and ESD protection standards.

Highest-signal resume keywords

Custom IC Layout ExperienceHigh-Frequency Mixed-Signal Circuit DesignHierarchical Block IntegrationAdvanced CMOS/FinFET Node ExperienceLayout-Dependent Effects Knowledge

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Physical Silicon Layout DesignBlock-Level Floor Plan CreationChip-Top-Level Floor Plan CreationMicro-Bump Co-DesignDevice Matching TechniquesCommon-Centroid StructuresGuard Rings ImplementationIsolation TechniquesDRC ClosureLVS Closure

Certifications & Qualifications

Bachelor's Degree

Industry Keywords

SerDesADCsDACsPLLsDeep Sub-Micron NodesTSMC N3TSMC N5TSMC N7EM/IR ReliabilityESD Protection

About the role

Key responsibilities & impact

Design physical silicon layouts for high-frequency or high-speed mixed-signal circuits, including SerDes, ADCs, DACs, PLLs, and high-speed blocks
Create block-level and chip-top-level floor plans
Manage hierarchical block integration
Handle micro-bump or package-aware co-design
Address layout-dependent effects, including LOD, WPE, and LDE
Implement device matching and common-centroid structures
Implement guard rings and isolation or shielding, including coaxial, differential, and ground shields
Ensure closure on DRC, LVS, ERC, antenna rules, EM/IR reliability, and ESD protection
Travel to an Arrow Client office location when requested by Arrow Client leadership

Requirements

What you’ll need

Bachelor’s degree
Generally 5 to 12+ years of hands-on custom IC layout experience
Experience in deep sub-micron or advanced CMOS/FinFET nodes, such as TSMC N3, N5, and N7
Experience at lower nodes (N3, N5) is critical
Ability to design physical silicon layout for high-frequency or high-speed mixed-signal circuits, including SerDes, ADCs, DACs, PLLs, and high-speed blocks
Ability to create block-level and chip-top-level floor plans
Experience with hierarchical block integration
Experience with micro-bump or package-aware co-design
Knowledge of layout-dependent effects (LOD, WPE, LDE)
Knowledge of device matching and common-centroid structures
Knowledge of guard rings and isolation or shielding techniques, including coaxial, differential, and ground shields
Experience ensuring closure on DRC, LVS, ERC, antenna rules, EM/IR reliability, and ESD protection
Must be able to travel to an Arrow Client office location as requested by Arrow Client leadership
Must be able to work in the US-TX/Texas Central Time Zone

Benefits

Comp & perks

Remote work arrangement
Full-time employment
Potential to work remotely within the United States
Equal opportunity employment