Principal ASIC Verification Engineer

Atom Computing

. Own block-to-chip verification plans, schedules, and signoff criteria; lead test development and execution .

Posted 10/8/2026full-timeAustin • Texas • United StatesLead💰 $180,000 - $220,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates extensive expertise in ASIC/SoC verification, including block-to-chip verification, test development, and execution. Proficient in Python and SystemVerilog for creating reusable testbenches and conducting thorough verification processes.

Highest-signal resume keywords

ASIC/SoC Verification ExperiencePython Testbench DevelopmentSystemVerilog AssertionsDFT Verification ExperiencePost-Layout Gate-Level Verification

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

ASIC VerificationSoC VerificationPython ProgrammingSystemVerilogRTL DebuggingBehavioral ModelingRegression AutomationTiming SimulationDFT TechniquesCoverage Closure

Soft Skills

Technical DirectionMentoringCommunication

Tools & Technologies

UVMHDL Debug ToolsLinuxVersion Control

Industry Keywords

TapeoutSilicon ValidationMixed-Signal BlocksDesign RequirementsTest Modes

Tech Stack

Tools & technologies

LinuxPython

About the role

Key responsibilities & impact

Own block-to-chip verification plans, schedules, and signoff criteria; lead test development and execution
Provide technical direction, mentor engineers, review test plans and code, and participate in candidate interviews
Define contractor scope, milestones, and acceptance criteria; review deliverables and oversee integration and handoff
Develop Python testbenches, reusable drivers, monitors, reference models, and scoreboards integrated with RTL simulators
Implement tests, automate regressions, debug failures, and close coverage
Communicate verification status, unresolved defects, and tapeout risks
Lead post-layout gate-level verification, including netlist preparation, SDF annotation, and timing-accurate simulation
Verify test modes and patterns with DFT, design, and physical design teams; resolve timing and signoff issues
Resolve requirements and interface issues with architecture, RTL, firmware, and hardware teams
Support silicon bring-up and validation

Requirements

What you’ll need

Bachelor's degree in electrical engineering, computer engineering, computer science, or a related field, or equivalent experience
10+ years of ASIC/SoC verification experience, with 15+ preferred
Experience verifying multiple ASICs through tapeout and subsequent silicon evaluation
Experience with block-to-chip verification of registers, data paths, and firmware interfaces
Strong Python skills for reusable, object-oriented testbenches with constrained-random stimulus, simulation control, checkers, and coverage
Ability to build behavioral models of mixed-signal blocks, including digital interfaces and timing
Experience turning design requirements into verification plans
Experience writing SystemVerilog assertions and closing functional and code coverage
Hands-on post-P&R experience preparing netlists and cell/memory models, annotating SDF, and debugging timing simulations
DFT verification experience with scan shift/capture, ATPG patterns, MBIST, or JTAG
Strong RTL and waveform debugging skills, especially resets, clock domains, X propagation, and timing checks
Proficiency with SystemVerilog/UVM, HDL debug tools, Linux, and version control
Experience with regression automation, failure reproduction, and triage

Benefits

Comp & perks

Fully paid medical, dental, and vision insurance for employees and dependents
Unlimited paid time off
401K company matching
Short- and long-term disability
FSA
Dependent care benefits
Life insurance
Drinks, snacks, and catered team lunches in the offices every day
Annual bonus
Equity in the company