Principal PLL IC Design Engineer, TeraWave

BLUE ORIGIN

. Lead design, development, and integration of PLLs and clock distribution in advanced CMOS FinFET and SiGe technologies .

Posted 9/30/2026full-timeUnited StatesLead💰 $269,175 - $376,844 per yearWebsite

Core Competencies

Role fit

Core Competencies

Use this summary to align your resume positioning with the role.

Demonstrates expertise in designing and developing high-speed PLLs and clock distribution circuits for RF and mmWave applications, with a strong focus on performance optimization and integration. Proficient in mixed-mode and RF modeling, simulation, and verification using industry-standard tools.

Highest-signal resume keywords

High-Speed PLL DesignRF and mmWave ApplicationsMixed-Mode and RF ModelingAnalog/RF Building Blocks DesignClock Domain Synchronization

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

PLL Circuit DesignClock DistributionPhase Noise/Jitter OptimizationSilicon CharacterizationDebuggingMATLABSpectreSystemVerilogAMSAnalog Design Best Practices

Soft Skills

MentoringCollaboration

Certifications & Qualifications

Bachelor's Degree in Electrical EngineeringBlue's Standard Background Check

Industry Keywords

CMOS FinFETSiGe TechnologiesRF PayloadsHigh-Performance CircuitsAnalog Building Blocks

About the role

Key responsibilities & impact

Lead design, development, and integration of PLLs and clock distribution in advanced CMOS FinFET and SiGe technologies
Optimize performance and analyze design trade-offs
Develop high-performance PLL circuits using Spectre and AMS flows
Collaborate with RF and SoC system architects to define PLL and sub-block requirements
Integrate PLLs into RF payloads and terminals
Oversee layout, top-level integration, floorplanning, and verification through tape-out
Work with validation and product engineers to develop test plans, facilitate bring-up, optimize performance, and support reliable, high-yield production
Investigate and implement analog building blocks to improve circuit performance
Mentor junior engineers on analog design best practices
Travel up to 10% of the time

Requirements

What you’ll need

Bachelor's degree in Electrical Engineering or related technical discipline
10+ years of experience designing and developing high-speed (>20GHz) PLLs and LO generation for high-performance RF and mmWave applications
Expertise in loop design for phase noise/jitter, spur profile, area, and power optimization
Proficiency designing PLLs and clock distribution circuits for wireless and wireline applications
Experience with clock domain synchronization techniques involving multiple PLLs and/or clock domains
Fundamental understanding of device physics for process selection and performance optimization
Full proficiency in mixed-mode and RF modeling, simulation, and verification using MATLAB, Spectre, SystemVerilog, and AMS
Extensive experience in PLL silicon characterization and debugging
Proficiency designing analog/RF building blocks, including amplifiers, filters, mixers, harmonic-rejection mixers, pre-scalers, and frequency multipliers
Must be a U.S. citizen or national, U.S. permanent resident/current Green Card holder, or lawfully admitted refugee or granted asylee
Must complete Blue's Standard Background Check
Technical assessment required during interviews

Benefits

Comp & perks

Relocation provided
Medical, dental, and vision insurance
Basic and supplemental life insurance
Paid parental leave
Short- and long-term disability
401(k) with company match of up to 5%
Education Support Program
Stock options for all regular employees working at least 20 hours/week
Up to four weeks of paid time off per year based on weekly scheduled hours
Up to 14 company-paid holidays
Potential benefits and bonuses based on role type, job level, individual contributions, company results, or other factors