Senior ASIC Design Engineer

BLUE ORIGIN

. Design and develop FPGAs, digital ASICs, and/or mixed-signal ASICs .

Posted 11/5/2026full-timeUnited StatesSenior💰 $249,235 - $348,929 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in FPGA and ASIC design, including proficiency in HDL programming with VHDL, Verilog, and SystemVerilog. Capable of developing verification methodologies, conducting timing analysis, and collaborating effectively with cross-functional teams.

Highest-signal resume keywords

ASIC Design And ImplementationHDL Programming (VHDL, Verilog, SystemVerilog)Design Verification And Test Bench DevelopmentLinux Development EnvironmentExperience With Software-Defined Radio Architectures

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

FPGA DesignDigital ASIC DesignMixed-Signal ASIC DesignTiming AnalysisNoise AnalysisTest Plan DevelopmentCoverage ModelsObject-Oriented Programming (Python, TCL, Perl)DFT/Scan/MBIST/LBIST MethodologiesRTL2GDSII Physical Design

Soft Skills

CollaborationProblem-SolvingMentoring

Tools & Technologies

EDA ToolsTest HarnessesLab Integration Tools

Certifications & Qualifications

U.S. Citizenship Or NationalityU.S. Permanent ResidencyBlue’s Standard Background Check

Industry Keywords

DSPCommunications SystemsSpread SpectrumForward Error CorrectionModulation Types (QPSK, QAM, PCM/FM, PAM)Deep Sub-Micron FinFETCMOS Technologies

Tech Stack

Tools & technologies

DACLinuxPerlPython

About the role

Key responsibilities & impact

Design and develop FPGAs, digital ASICs, and/or mixed-signal ASICs
Implement designs using HDL, including VHDL, Verilog, and/or SystemVerilog
Develop verification methodologies and test benches for block- and system-level verification
Create and execute test plans, develop test harnesses, and implement coverage models
Conduct timing analysis, noise analysis, and other signoff checks
Collaborate with systems, firmware, architecture, and product engineering teams
Support lab integration and troubleshooting activities
Resolve design issues and drive solutions for timing, congestion, and other implementation challenges
Contribute to TeraWave, Blue Origin’s satellite communications network

Requirements

What you’ll need

7+ years of experience in ASIC design and implementation
Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical discipline
Experience with FPGA and ASIC design
Proficiency in HDL programming (VHDL, Verilog, and/or SystemVerilog)
Experience with Linux development environment
Experience with design verification and test bench development
U.S. citizenship or nationality, U.S. permanent residency, or lawful admission to the U.S. as a refugee or asylee
Required Blue’s Standard Background Check
Advanced degree (MS/PhD) in Electrical Engineering, Computer Engineering, or related field preferred
Experience in full ASIC/FPGA lifecycle preferred
Experience with Software-Defined Radio Architectures, ADC/DAC, and/or DSPs preferred
Knowledge of DSP and communications systems, including spread spectrum, forward error correction, and modulation types (QPSK, QAM, PCM/FM, PAM) preferred
Strong object-oriented programming and scripting skills (Python, TCL, Perl) preferred
Experience with physical design flows and industry-standard EDA tools preferred
Experience with RTL2GDSII physical design and signoff flows preferred
Knowledge of deep sub-micron FinFET and CMOS technologies preferred
Experience with DFT/Scan/MBIST/LBIST methodologies preferred
Experience mentoring junior engineers preferred

Benefits

Comp & perks

Medical, dental, vision, basic and supplemental life insurance
Paid parental leave
Short- and long-term disability
401(k) with a company match of up to 5%
Education Support Program
Stock Options for all regular employees working at least 20 hours/week
Paid Time Off: up to four weeks per year based on weekly scheduled hours
Up to 14 company-paid holidays
Potential benefits and bonuses based on role type, job level, individual contributions, and company results; amounts and eligibility are not guaranteed
Temporary remote work exception while local sites are being developed in San Diego and Austin