Senior ASIC Design Verification Engineer

BLUE ORIGIN

. Own verification planning and execution for complex blocks and subsystems from test plan through sign-off .

Posted 10/19/2026full-timeUnited StatesSenior💰 $230,398 - $322,557 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in ASIC and SoC functional verification, including hands-on experience with SystemVerilog and UVM. Capable of developing verification strategies, building verification infrastructure, and mentoring junior engineers in verification methodologies.

Highest-signal resume keywords

ASIC Functional VerificationSystemVerilog ExpertiseUVM Testbench DevelopmentMetric-Driven VerificationAI-Assisted Verification

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Verification PlanningConstrained-Random SimulationFormal AnalysisFunctional Coverage ClosureDebug MethodologyDigital Control Logic VerificationDatapath Logic VerificationAssertions DevelopmentRegression Health ManagementMixed-Signal Interfaces

Soft Skills

MentoringCollaboration

Tools & Technologies

Verification EnvironmentsCI SystemsReference ModelsProtocol MonitorsScoreboards

Industry Keywords

SoC VerificationDSP HardwareWireless CommunicationsModemFECLDPCBeamforming LogicInterconnect VerificationFault ToleranceReliability Verification

About the role

Key responsibilities & impact

Own verification planning and execution for complex blocks and subsystems from test plan through sign-off
Translate design specifications into verification strategies, measurable coverage goals, and early identification of high-risk scenarios
Select verification methods including constrained-random simulation, formal analysis, and directed testing
Develop verification environments, reference models, scoreboards, protocol monitors, coverage components, and assertions
Drive functional coverage closure, regression health, and sign-off readiness across simulation and formal results
Build verification infrastructure, regression and CI systems, and reuse strategy across IP, subsystem, and SoC levels
Apply and build AI-assisted verification capabilities for stimulus generation, regression triage, and coverage analytics
Review testbench architecture and debug methodology
Mentor junior engineers in verification methodology
Contribute to TeraWave's first in-house silicon program, including a high-throughput modem and DSP-intensive digital beamformer targeted for first tapeout in 2027
Work across IP, subsystem, and full SoC verification, including CPU subsystems, interconnects, security, peripherals, modem datapath and PHY layers, DSP and beamforming compute, and mixed-signal interfaces

Requirements

What you’ll need

Bachelor's degree in Electrical Engineering, Computer Engineering, or related field, or equivalent experience
Minimum five years of professional experience in ASIC or SoC functional verification
Hands-on expertise in SystemVerilog
Experience with UVM or formal testbench development and maintenance
Experience with metric-driven verification for planning, assertions, and functional coverage closure
Experience verifying complex digital control and datapath logic, including RTL and system-level debug
U.S. citizen or national, U.S. permanent resident/current Green Card holder, or lawfully admitted into the U.S. as a refugee or granted asylum
Standard background check required
Preferred: background in space-based communications, wireless communications, modem, baseband, or DSP hardware
Preferred: experience verifying LDPC, FEC, framing, or beamforming logic using bit-accurate reference models and fixed-point analysis
Preferred: formal verification experience on production silicon
Preferred: interconnect or NoC verification experience
Preferred: fault tolerance and reliability verification experience
Preferred: C-based or portable stimulus experience for SoC, CPU boot, and firmware-driven test scenarios
Preferred: experience applying AI, ML, or LLM tooling to verification

Benefits

Comp & perks

Medical, dental, and vision insurance
Basic and supplemental life insurance
Paid parental leave
Short- and long-term disability
401(k) with company match of up to 5%
Education Support Program
Stock options for all regular employees working at least 20 hours/week
Up to four weeks of paid time off per year based on weekly scheduled hours
Up to 14 company-paid holidays
Potential benefits and bonuses based on role type, job level, individual contributions, and company results