Design-for-Test Engineer – ASIC Backend, Associate/Experienced/Lead

Boeing

. Design and implement DFT architectures including TAP/JTAG, IJTAG, Boundary Scan, MBIST, and scan compression .

Posted 11/10/2026full-timeEl Segundo • California • United StatesSenior💰 $98,600 - $197,800 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in Design for Testability (DFT) methodologies, including TAP/JTAG, IJTAG, and Boundary Scan, with a strong foundation in ASIC/logic design flow and HDL programming. Proficient in DFT verification methodologies and scripting languages such as Tcl, Perl, or Python, while ensuring compliance with U.S. security clearance requirements.

Highest-signal resume keywords

Design For Testability (DFT)TAP/JTAGIJTAG (IEEE 1687)HDL (Verilog/SystemVerilog)DFT Verification Methodologies

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Applicant Tracking System Keywords

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Hard Skills

ASIC/Logic Design FlowStatic Timing AnalysisECO ProcessesBoundary Scan (IEEE 1149.1)MBISTScan CompressionATPGSilicon DebugPattern GenerationCoverage Optimization

Soft Skills

CollaborationCommunication

Tools & Technologies

TclPerlPython

Certifications & Qualifications

U.S. Security ClearanceU.S. Secret Clearance

Industry Keywords

AerospaceSpace-System ProductsConflict of Interest (COI)U.S. Export Control Compliance

Tech Stack

Tools & technologies

PerlPython

About the role

Key responsibilities & impact

Design and implement DFT architectures including TAP/JTAG, IJTAG, Boundary Scan, MBIST, and scan compression
Develop and validate TAP/JTAG and IJTAG infrastructures, BSDL/ICL/PDL artifacts, and ATPG pattern generation
Drive pattern generation, coverage optimization, memory test validation, and silicon debug
Integrate DFT features across the chip design flow
Collaborate with cross-functional teams to ensure robust DFT integration
Coordinate with external partners and customers on custom DFT interfaces and security requirements
Contribute to DFT methodologies for next-generation aerospace and space-system products
Participate in occasional travel and after-hours meetings during critical milestones

Requirements

What you’ll need

U.S. Citizenship required for ability to obtain a U.S. Security Clearance
Interim and/or final U.S. Secret Clearance Post-Start required
U.S. Person required for U.S. export control compliance
Bachelor of Science degree in Engineering, Computer Science, Data Science, Mathematics, Physics, Chemistry, or non-US equivalent qualifications directly related to the work statement
2+ years of experience in Design for Testability (DFT) or equivalent
Strong knowledge of ASIC/logic design flow, HDL (Verilog/SystemVerilog), static timing analysis, and ECO processes
Hands-on expertise with TAP/JTAG, IJTAG (IEEE 1687), Boundary Scan (IEEE 1149.1), MBIST, scan compression, ATPG, at-speed test, and silicon debug
Proficiency in Tcl, Perl, or Python scripting and DFT verification methodologies
Ability to satisfy the Company’s Conflict of Interest (COI) assessment process
Employer will not sponsor applicants for employment visa status
Experienced, Level 3: 5+ years of related engineering experience preferred
Lead, Level 4: 9+ years of related engineering experience preferred
Bachelor’s or Master’s Degree in EE, Computer Engineering/Science, or related field preferred
ABET accreditation preferred, but not required

Benefits

Comp & perks

Strong work–life balance
Relocation based on candidate eligibility
Health insurance
Flexible spending accounts
Health savings accounts
Retirement savings plans
Life and disability insurance programs
Paid and unpaid time away from work
Variable compensation opportunities
1st shift