Design-for-Test Engineer – ASIC Backend – Associate, Experienced, Lead

Boeing

. Design and implement DFT architectures including TAP/JTAG, IJTAG, Boundary Scan, MBIST, and scan compression .

Posted 11/10/2026full-timeEl Segundo • California • United StatesSenior💰 $98,600 - $197,800 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in Design for Testability (DFT) methodologies, including TAP/JTAG, IJTAG, and Boundary Scan, while ensuring robust integration across chip design flows in aerospace environments. Proficient in scripting languages such as Tcl, Perl, or Python for DFT verification and pattern generation.

Highest-signal resume keywords

Design For Testability (DFT)TAP/JTAG ExpertiseHDL (Verilog/SystemVerilog)Silicon DebugUS Security Clearance

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

DFT MethodologiesBoundary Scan (IEEE 1149.1)MBISTATPGScan CompressionStatic Timing AnalysisECO ProcessesPattern GenerationTcl ScriptingPerl Scripting

Soft Skills

CollaborationCommunication

Certifications & Qualifications

Bachelor of Science DegreeUS Security Clearance

Industry Keywords

Aerospace ProductsASIC/Logic Design FlowCross-Functional TeamsCustom DFT InterfacesExport Control Compliance

Tech Stack

Tools & technologies

PerlPython

About the role

Key responsibilities & impact

Design and implement DFT architectures including TAP/JTAG, IJTAG, Boundary Scan, MBIST, and scan compression
Develop and validate TAP/JTAG and IJTAG infrastructures, BSDL/ICL/PDL artifacts, and ATPG pattern generation
Drive pattern generation, coverage optimization, memory test validation, and silicon debug
Integrate DFT features across the chip design flow
Collaborate with cross-functional teams to ensure robust DFT integration
Coordinate with external partners and customers on custom DFT interfaces and security requirements
Contribute to DFT methodologies for next-generation aerospace products
Support advanced digital subsystem development in an aerospace environment

Requirements

What you’ll need

Ability to obtain a US Security Clearance; U.S. Citizenship required as a condition of employment
Interim and/or final U.S. Secret Clearance required post-start
U.S. Person status required for U.S. export control compliance
Bachelor of Science degree in a specified technical field or non-US equivalent qualifications directly related to the work statement
2+ years of experience in Design for Testability (DFT) or equivalent
Strong knowledge of ASIC/logic design flow, HDL (Verilog/SystemVerilog), static timing analysis, and ECO processes
Hands-on expertise with TAP/JTAG, IJTAG (IEEE 1687), Boundary Scan (IEEE 1149.1), MBIST, scan compression, ATPG, at-speed test, and silicon debug
Proficiency in Tcl, Perl, or Python scripting and DFT verification methodologies
Ability to satisfy the Company’s Conflict of Interest assessment process
Must work 100% onsite at one of the listed locations
Employer will not sponsor applicants for employment visa status
Occasional travel and after-hours meetings during critical milestones
Experienced Level 3: 5+ years of related engineering experience
Lead Level 4: 9+ years of related engineering experience

Benefits

Comp & perks

Competitive base pay
Variable compensation opportunities
Health insurance
Flexible spending accounts
Health savings accounts
Retirement savings plans
Life and disability insurance programs
Paid and unpaid time away from work
Relocation based on candidate eligibility
1st shift schedule
Strong work–life balance