ASIC DFT Engineer

Broadcom

. Lead DFT programs from chip-level specification through implementation, verification, and product release to production .

Posted 11/11/2026full-timeUnited StatesSeniorLead💰 $109,700 - $175,500 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in DFT architecture and implementation, including Scan, BIST, and ATPG, while effectively collaborating with cross-functional teams to enhance silicon yield and quality. Proficient in EDA tools and scripting for automation, with a strong foundation in digital and analog circuit design.

Highest-signal resume keywords

DFT Architecture ImplementationEDA Tools ProficiencyVerilog CodingSilicon Yield ImprovementCross-Functional Communication

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

DFT ArchitectureScan InsertionATPG Pattern GenerationTestbench DevelopmentMemory BIST StrategiesDigital Circuit DesignAnalog Circuit DesignDevice PhysicsScripting in PythonScripting in TCL

Soft Skills

Problem-SolvingProject ManagementEffective Communication

Tools & Technologies

DFT CompilerTestKompressTetraMaxFastScanATE TestingSerDesDDRPCIeEthernetCXL

Industry Keywords

SoC DFT ActivitiesPost-Silicon DebugYield ImprovementSilicon ManufacturingStatistical Process Control

Tech Stack

Tools & technologies

PythonC++

About the role

Key responsibilities & impact

Lead DFT programs from chip-level specification through implementation, verification, and product release to production
Participate in all phases of SoC DFT activities, including DFT architecture, test insertion, verification, pattern generation, coverage improvement, post-silicon debug, and yield improvement
Define DFT specifications based on Broadcom and customer DFT feature requirements and DPPM goals
Implement DFT architectures including Scan, MBIST, TAP, LBIST, IO, SerDes, and IP DFT integration
Perform ASIC/chip-level ATPG and verification and rapidly bring up ATE test patterns
Collaborate with STA and design integration engineers on timing and design closure
Generate, verify, and debug test vectors before tapeout release
Validate and debug test vectors on ATE during silicon bring-up
Assist with silicon failure analysis, diagnostics, and yield improvement
Interface with customers, physical design teams, and global test engineering/manufacturing teams
Work with IP DFT engineers and cross-functional stakeholders
Debug customer-returned parts (RMA) on ATE
Develop innovative DFT solutions for advanced process nodes (3nm and beyond)
Automate DFT and test vector generation flows

Requirements

What you’ll need

Bachelors in Electrical/Electronic/Computer Engineering and 8+ years of relevant industry experience, or Masters Degree in Electrical/Electronic/Computer Engineering and 6+ years of relevant industry experience
Strong DFT architecture and implementation background, including Scan, BIST, IO/Analog DFT, IJTAG/IEEE 1687, and IEEE 1149.1/1149.6
Proficiency with EDA tools for scan insertion, compression, and ATPG, such as DFT Compiler, TestKompress, TetraMax, and FastScan
Hands-on experience with memory and logic BIST strategies, verification, and debug across embedded memories including SRAM, CAM, RF, and ROM
Experience with In-Field testing solutions is a plus
Extensive experience in Verilog coding, testbench development, ATPG pattern generation, simulation, and timing constraints/Test-STA
Strong foundation in digital/analog circuit design, device physics, silicon manufacturing, synthesis, and transistor reliability
Strong problem-solving, root-cause debug, statistical process control, and data analysis skills for silicon yield and quality improvement
Effective cross-functional communication and project management skills
Experience with ATE silicon bring-up, debug, and high-speed IP/interface testing such as SerDes, DDR, PCIe, Ethernet, CXL, and Tessent SSN is a plus
Proficiency in scripting and automation using Python, TCL, or C++, with emphasis on AI-augmented development

Benefits

Comp & perks

Discretionary annual bonus
Competitive new hire equity grant
Annual equity awards
Medical, dental and vision plans
401(K) participation including company matching
Employee Stock Purchase Program (ESPP)
Employee Assistance Program (EAP)
Company paid holidays
Paid sick leave and vacation time
Paid Family Leave and other leaves of absence