ASIC Package Design Engineer

Broadcom

. Own overall design responsibility for ASIC package designs, including signal integrity, power integrity, manufacturability, reliability, and thermal considerations .

Posted 10/20/2026full-timeUnited StatesSeniorLead💰 $143,800 - $230,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates extensive expertise in ASIC package design, focusing on signal integrity, power integrity, and manufacturability, while effectively managing multiple projects and collaborating with global teams.

Highest-signal resume keywords

ASIC Package DesignSignal IntegrityPower IntegrityCadence APD ExperienceFlip-Chip BGA Package Design

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Flip-Chip BGA Package DesignSignal Integrity AnalysisPower Integrity AnalysisPhysical Design LayoutProcess DevelopmentDesign AutomationHigh-Speed SerDes DesignProject ManagementThermal ConsiderationsReliability Engineering

Soft Skills

Self-ManagementOrganization SkillsCollaborationCustomer Interface

Tools & Technologies

Cadence APDAllegro Package DesignerCadence SKILL

Certifications & Qualifications

BSEEMSEE

Industry Keywords

AINetworkingHPC5G Base StationsDesign Automation

Tech Stack

Tools & technologies

DAC

About the role

Key responsibilities & impact

Own overall design responsibility for ASIC package designs, including signal integrity, power integrity, manufacturability, reliability, and thermal considerations
Design critical package structures for SerDes, ADC/DAC, DDR, HBM, and related technologies
Schedule, prioritize, and track work across 2+ projects simultaneously
Perform general flip-chip BGA package design and engineering
Manage projects and serve as customer interface for design projects
Contribute to design-team efficiency through process development and improvement, automation, and documentation
Perform physical design (layout) as a foundational responsibility
Collaborate with a worldwide R&D team developing high-performance ASIC packages for AI, networking, HPC, and 5G base stations

Requirements

What you’ll need

BSEE or similar field and 12+ years’ experience in flip-chip-BGA package design, including high-speed SerDes, OR MSEE or similar field and 10+ years’ work experience
Knowledge of package-level signal integrity and power integrity
Cadence APD (Allegro Package Designer) experience preferred; equivalent tool acceptable
Ability to cooperate with a worldwide team across multiple time zones, including co-design with internal team members and external vendor designers
Self-management and organization skills
Preferred: 1 or more years’ experience with Cadence SKILL for Allegro, or similar design-automation coding experience and interest
Must work on-site at the Broadcom office 5 days a week; not a remote-work position

Benefits

Comp & perks

Discretionary annual bonus
Competitive new hire equity grant
Annual equity awards
Medical, dental and vision plans
401(K) participation including company matching
Employee Stock Purchase Program (ESPP)
Employee Assistance Program (EAP)
Company paid holidays
Paid sick leave and vacation time
Paid Family Leave and other leaves of absence in accordance with applicable laws