ASIC Verification Engineer

Broadcom

. Design, implement, and maintain advanced verification infrastructure across a diverse portfolio of ASIC products .

Posted 11/7/2026full-timeFort Collins • Colorado • United StatesMid-LevelSenior💰 $109,700 - $175,500 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates extensive expertise in ASIC verification, including proficiency in SystemVerilog, UVM, and the complete ASIC design lifecycle. Capable of developing and executing comprehensive verification plans and testbenches while optimizing coverage metrics and managing design database processes.

Highest-signal resume keywords

SystemVerilog ProficiencyUniversal Verification Methodology (UVM)ASIC Verification ExperienceC/C++ Programming SkillsPython Scripting Expertise

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

SystemVerilogVerilogSystemVerilog Assertions (SVA)Universal Verification Methodology (UVM)C/C++ ProgrammingPython ScriptingPerl ScriptingTcl ScriptingDigital Signal Processing (DSP)Coverage Closure

Industry Keywords

ASIC DesignFront-to-Back Verification LifecycleARM Processor ArchitecturesAMBA Subsystem ProtocolsAXIAHBAPB

Tech Stack

Tools & technologies

PerlPythonC++

About the role

Key responsibilities & impact

Design, implement, and maintain advanced verification infrastructure across a diverse portfolio of ASIC products
Collaborate with design teams to develop exhaustive verification plans
Construct reusable testbenches using SystemVerilog and UVM
Architect modular verification components, including reference models, checkers, monitors, scoreboards, and targeted firmware code
Analyze architectural specifications and author detailed verification plans
Develop, execute, and debug directed and constrained-random test cases for complex ASIC IP blocks
Track, analyze, and maximize functional and code coverage metrics
Write SystemVerilog Assertions (SVA) for assertion-based verification and corner-case bug detection
Establish, maintain, and optimize processes for design database management and official database releases
Oversee automated daily and weekly regression runs, triage failures, and manage performance tracking

Requirements

What you’ll need

Bachelor’s Degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field with a minimum of 8 years of relevant ASIC verification experience OR Master’s Degree in a related field with a minimum of 6 years of relevant ASIC verification experience
Strong proficiency in SystemVerilog, Verilog coding, and SystemVerilog Assertions (SVA)
Hands-on experience building testbenches from scratch using the Universal Verification Methodology (UVM)
Deep understanding of the front-to-back ASIC design and verification lifecycle, including pre-silicon simulation, debugging, and coverage closure
Familiarity with ARM processor architectures and AMBA subsystem protocols, such as AXI, AHB, and APB
Exposure to Digital Signal Processing (DSP) algorithms and translating them into hardware verification reference models
Strong programming skills in C/C++
Scripting expertise in Python, Perl, or Tcl for environment automation and regression sorting

Benefits

Comp & perks

Discretionary annual bonus
Competitive new hire equity grant
Annual equity awards
Medical plans
Dental plans
Vision plans
401(K) participation including company matching
Employee Stock Purchase Program (ESPP)
Employee Assistance Program (EAP)
Company paid holidays
Paid sick leave
Vacation time
Paid Family Leave and other leaves of absence in accordance with applicable laws