Design Implementation Engineer

Broadcom

. Perform design implementation activities related to place and route and/or timing closure .

Posted 10/20/2026full-timeUnited StatesMid-LevelSenior💰 $121,900 - $195,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates extensive expertise in design implementation activities for ASIC/SoC, focusing on timing analysis, place and route, and physical verification. Proficient in utilizing industry-standard tools and methodologies to achieve optimal PPA metrics and ensure successful tapeout.

Highest-signal resume keywords

Design Implementation ActivitiesTiming AnalysisPlace And Route ToolsPhysical VerificationTapeout Experience

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Floor-PlanningPartitioningPlacementClock Tree SynthesisRoutingTiming ClosureStatic Timing AnalysisPower OptimizationECO ImplementationFormal Verification

Soft Skills

Excellent Communication SkillsAbility To Work IndependentlyAdaptability To New Tools

Tools & Technologies

PrimetimeICC2InnovusCaliberLEC

Industry Keywords

ASICSoC7nm TechnologyPPA MetricsLVSDRC

About the role

Key responsibilities & impact

Perform design implementation activities related to place and route and/or timing closure
Execute floor-planning, partitioning, placement, clock tree synthesis, routing, timing analysis, timing closure and physical verification (LVS/DRC)
Drive tools and methodologies to achieve desired PPA metrics
Perform equivalence checks, static timing analysis, timing closure and power optimization
Implement timing and functional ECOs
Apply Broadcom’s design methodology and milestone flow to meet criteria for right-first-time silicon
Work primarily in place and route and/or timing, including constraints and STA

Requirements

What you’ll need

Extremely proficient in design implementation activities at block and SoC level
Experience with floor-planning, partitioning, placement, clock tree synthesis, route, physical verification, constraints development, constraints validation, timing analysis and closure
Experience with formal verification, timing analysis and ECO implementation
Experience with Primetime, ICC2, Innovus, Caliber, LEC and PrimeTime
Full chip tapeout experience based on 7nm and lower technologies highly preferred
Hands-on experience with timing analysis and place and route tools for ASIC/SoC design
Tapeout experience on at least 1–2 ASICs in 7nm or lower technologies
BS in Electrical Engineering, Computer Engineering or related field and 8+ years of related experience, or MS in Electrical Engineering, Computer Engineering or related field and 6+ years of related experience
Ability to work independently and in a global, dynamic environment
Ability to learn and adapt to new tools and methodologies
Excellent communication skills

Benefits

Comp & perks

Discretionary annual bonus
Competitive new hire equity grant
Annual equity awards
Medical, dental and vision plans
401(K) participation including company matching
Employee Stock Purchase Program (ESPP)
Employee Assistance Program (EAP)
Company paid holidays
Paid sick leave
Vacation time
Paid Family Leave and other leaves of absence in accordance with applicable laws