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Broadcom

Design Implementation Engineer – Synthesis, STA

Broadcom

. Lead and execute synthesis, static timing analysis, formal verification, and low-power implementation activities for mixed-signal blocks .

Posted 11/11/2026full-timeUnited StatesMid-LevelSenior💰 $121,900 - $195,000 per yearWebsite

Core Competencies

Role fit
Core Competencies

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Demonstrates expertise in synthesis, static timing analysis, and formal verification for mixed-signal blocks, with a strong focus on low-power design methodologies and automation tools. Proven ability to collaborate effectively across global design and physical implementation teams while ensuring high-quality results and successful IP deployment.

Highest-signal resume keywords
Synthesis ExpertiseStatic Timing Analysis (STA)Formal VerificationLow-Power Design Methodologies (UPF/CPF)Automation Tool Development (Tcl, Perl, Python)

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills
SynthesisStatic Timing AnalysisFormal VerificationLow-Power ImplementationTiming Constraints CreationTiming Signoff MethodologiesQuality of Results (QoR) EvaluationTiming and Functional ECOs GenerationPhysical Design ImplementationRTL Design and Architecture
Soft Skills
Analytical MindsetProblem-Solving SkillsAttention to DetailEffective Communication
Tools & Technologies
Design CompilerGenusPrimeTimeTempusFormalityVCLPGitDesignSyncCalibreICC2
Industry Keywords
Mixed-Signal BlocksIP Release OwnerCross-Functional CollaborationHigh-Complexity ASICs/SoCsTapeout

Tech Stack

Tools & technologies
PerlPython

About the role

Key responsibilities & impact
  • Lead and execute synthesis, static timing analysis, formal verification, and low-power implementation activities for mixed-signal blocks
  • Execute synthesis and run CDC, RDC, UPF/CPF power-intent static checks for digital/mixed-signal blocks
  • Create, validate, and maintain timing constraints
  • Perform STA and define timing signoff methodologies, including corners and derating
  • Run formal verification and logical equivalence checking throughout the design flow
  • Generate and implement timing and functional ECOs to drive timing closure
  • Evaluate pre- and post-route Quality of Results (QoR)
  • Serve as IP Release Owner and final gatekeeper for IP deployment
  • Drive release validation, audit files for synchronization gaps, and ensure proper revision-control tagging before handoff to customers or SoC teams
  • Build and deploy script-based automation for implementation and audit tasks
  • Collaborate as a cross-functional liaison between global design and physical implementation teams

Requirements

What you’ll need
  • BS in Electrical Engineering, Computer Engineering, or a related field with 8+ years of related experience, OR an MS with 6+ years of related experience
  • Extensive experience with high-complexity silicon in advanced technology nodes
  • Expertise in industry-standard tools for synthesis, STA, formal verification, and low-power audits, including Design Compiler, Genus, PrimeTime, Tempus, Formality, or VCLP
  • Hands-on experience with hardware data management tools such as Git, DesignSync, or equivalent
  • Strong familiarity with UPF/CPF low-power design methodologies
  • Experience developing custom automation tools using Tcl, Perl, or Python
  • Experience leveraging AI code-assist tools to accelerate script generation and code debugging
  • Strong analytical mindset, excellent problem-solving skills, and acute attention to detail
  • Effective communication skills for cross-functional liaison between global design and physical implementation teams
  • Direct experience with physical design implementation steps, including partitioning, floorplanning, placement, CTS, routing, and physical verification using tools such as Calibre, ICC2, or Innovus is a plus
  • Direct or indirect experience with RTL design and architecture is a plus
  • Contribution to successful tapeout or release deployment of at least 1–2 high-complexity ASICs/SoCs

Benefits

Comp & perks
  • Discretionary annual bonus
  • Competitive new hire equity grant
  • Annual equity awards
  • Medical, dental and vision plans
  • 401(K) participation including company matching
  • Employee Stock Purchase Program (ESPP)
  • Employee Assistance Program (EAP)
  • Company paid holidays
  • Paid sick leave
  • Vacation time
  • Paid Family Leave and other leaves of absence in accordance with applicable laws