IC Design Engineer

Broadcom

. Execute physical design, synthesis, physical verification, and timing closure .

Posted 10/20/2026full-timeUnited StatesSeniorLeadWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in physical design processes, including RTL synthesis, timing closure, and tape-out for PCIe Switch and Enterprise Storage products. Proficient in EDA tools and scripting languages, with strong collaboration and communication skills.

Highest-signal resume keywords

Physical Design ExpertiseRTL SynthesisTiming ClosureTCL/PERL ScriptingEDA Tools Proficiency

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Physical DesignSynthesisPhysical VerificationTiming ClosureEM/IR AnalysisPlace and RouteClock Tree SynthesisFloor-PlanningLayoutRTL-to-Silicon Tape-Out

Soft Skills

Excellent Verbal CommunicationExcellent Written Communication

Certifications & Qualifications

Bachelor’s Degree in Electrical EngineeringBachelor’s Degree in Electronics Engineering

Industry Keywords

PCIe SwitchEnterprise StorageAI/ML EcosystemsDatacentersTop-Level STACustom Clock TreesInsertion ReductionSkew BalancingFull Physical Design Cycle

Tech Stack

Tools & technologies

Perl

About the role

Key responsibilities & impact

Execute physical design, synthesis, physical verification, and timing closure
Set up and synthesize RTL
Perform timing closure through various methods and strategies
Conduct EM/IR analysis
Perform place and route
Execute clock tree synthesis
Perform floor-planning and layout
Develop flows and methodologies
Collaborate with IC Design RTL Engineers
Drive RTL-to-silicon tape-out for PCIe Switch and Enterprise Storage products supporting AI/ML ecosystems and datacenters

Requirements

What you’ll need

Bachelor’s degree required in Electrical Engineering or Electronics Engineering
8+ years of relevant experience
Knowledge and expertise in all Physical Design aspects of taking RTL to silicon tape-out
Experience with TCL/PERL scripting
Proficiency in related EDA tools
Full physical design cycle experience: RTL to tape-out
Experience in physical design, synthesis, physical verification, and timing closure
In-depth knowledge of top-level STA preferred
Experience with custom clock trees, insertion reduction, and skew balancing techniques
In-depth top-level floorplanning experience preferred
Excellent verbal and written communication skills

Benefits

Comp & perks

Discretionary annual bonus
Competitive new hire equity grant
Annual equity awards
Medical, dental and vision plans
401(K) participation including company matching
Employee Stock Purchase Program (ESPP)
Employee Assistance Program (EAP)
Company paid holidays
Paid sick leave
Vacation time
Paid Family Leave and other leaves of absence in accordance with applicable laws