IC Design Engineer

Broadcom

. Analyze high-level architecture specifications through interactive authoring and review .

Posted 9/28/2026full-timeUnited StatesSeniorLead💰 $143,800 - $230,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in Verilog/SystemVerilog RTL implementation and optimization, with a strong focus on high-performance design and debugging. Collaborates effectively with cross-functional teams to address complex design challenges and ensure timing closure.

Highest-signal resume keywords

Verilog/SystemVerilog RTL ImplementationRTL Optimization StrategiesRTL Debugging Skills12+ Years Industry ExperienceBachelor’s Degree in Engineering

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

RTL DesignHigh-Performance DesignTiming ClosureAsynchronous Clock Domain CrossingLow-Power DesignComplex AlgorithmsDeep ComputationsPipeliningMulti-Threaded DesignsThird-Party IP Integration

Tools & Technologies

Verification ToolsEmulation ToolsValidation Tools

Industry Keywords

PCIe ProtocolCXL ProtocolAMBA ProtocolsRAID Storage DesignsPCIe Switch Designs

About the role

Key responsibilities & impact

Analyze high-level architecture specifications through interactive authoring and review
Develop and document micro-architectures
Implement high-quality, high-performance Verilog/SystemVerilog RTL
Address asynchronous clock domain crossings, multiple power domains, low-power design, complex algorithms, deep computations and pipelining, multi-threaded designs, and third-party IP integration
Converge designs to timing closure through RTL optimization
Debug RTL and develop robust RTL solutions
Collaborate with Verification, Software/Firmware, Emulation, and Validation Engineering teams on RTL issues
Support silicon in the lab during validation

Requirements

What you’ll need

Bachelor’s degree required in Electrical Engineering, Electronics Engineering, Computer Science, Computer Engineering, or equivalent Engineering degree
12+ years of relevant industry experience
In-depth knowledge of implementing and supporting RTL designs using Verilog/SystemVerilog
High-quality, high-performance Verilog/SystemVerilog RTL implementation based on design specifications
RTL optimization strategies for timing closure
Superb RTL debugging skills
Must work in person; no remote work allowed
PCIe protocol, CXL protocol, AMBA protocols, RAID Storage designs, and PCIe Switch designs are desired but not required

Benefits

Comp & perks

Discretionary annual bonus
Competitive new hire equity grant
Annual equity awards
Medical, dental and vision plans
401(K) participation including company matching
Employee Stock Purchase Program (ESPP)
Employee Assistance Program (EAP)
Company paid holidays
Paid sick leave and vacation time
Paid Family Leave and other leaves of absence