IC Design Engineer

Broadcom

. Analyze high-level architecture specifications through interactive authoring and review .

Posted 10/23/2026full-timeUnited StatesSeniorLead💰 $143,800 - $230,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in Verilog/SystemVerilog RTL implementation and optimization, with a strong focus on timing closure and debugging. Capable of collaborating across engineering disciplines to support high-performance designs in AI/ML ecosystems and enterprise storage solutions.

Highest-signal resume keywords

Verilog/SystemVerilog RTL ImplementationRTL Optimization StrategiesRTL Debugging SkillsBachelor’s Degree in Engineering12+ Years of Relevant Industry Experience

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

RTL DesignMicro-Architecture DevelopmentAsynchronous Clock Domain CrossingLow-Power DesignComplex AlgorithmsDeep ComputationsPipeliningMulti-Threaded DesignsThird-Party IP IntegrationTiming Closure

Tools & Technologies

PCIe ProtocolCXL ProtocolAMBA ProtocolsRAID Storage DesignsPCIe Switch Designs

Industry Keywords

Electrical EngineeringElectronics EngineeringComputer ScienceComputer EngineeringSilicon ValidationVerification EngineeringSoftware/Firmware EngineeringEmulation EngineeringValidation EngineeringMega Datacenters

About the role

Key responsibilities & impact

Analyze high-level architecture specifications through interactive authoring and review
Develop and document micro-architecture
Implement Verilog/SystemVerilog RTL based on design specifications
Address asynchronous clock domain crossings, multiple power domains, low-power design, complex algorithms, deep computations and pipelining, multi-threaded designs, and third-party IP integration
Converge designs to timing closure through RTL optimization strategies
Debug RTL and develop robust RTL solutions
Work with Verification Engineering, Software/Firmware Engineering, Emulation Engineering, and Validation Engineering on RTL issues
Provide lab support as silicon progresses through validation
Drive next-generation AI/ML ecosystems through PCIe Switch Products and support Enterprise Storage Products for mega datacenters

Requirements

What you’ll need

Bachelor’s degree required in Electrical Engineering, Electronics Engineering, Computer Science, Computer Engineering, or equivalent Engineering degree
12+ years of relevant industry experience
In-depth knowledge of implementing and supporting RTL designs using Verilog/SystemVerilog
High-quality, high-performance Verilog/SystemVerilog RTL implementation
RTL optimization strategies for timing closure
Superb RTL debugging skills
Must work in person; no remote work allowed
Desired but not required: PCIe protocol
Desired but not required: CXL protocol
Desired but not required: AMBA protocols
Desired but not required: RAID Storage designs
Desired but not required: PCIe Switch designs

Benefits

Comp & perks

Discretionary annual bonus
Competitive new hire equity grant
Annual equity awards
Medical, dental and vision plans
401(K) participation including company matching
Employee Stock Purchase Program (ESPP)
Employee Assistance Program (EAP)
Company paid holidays
Paid sick leave
Vacation time
Paid Family Leave and other leaves of absence according to applicable laws