IC Design Engineer – STA, Synthesis

Broadcom

. Contribute to constraint development, constraint validation, synthesis, CDC audits, RDC audits, static equivalence audits, low-power audits, and timing closure of mission-critical IP and ASIC blocks in advanced technology nodes .

Posted 10/30/2026full-timeUnited StatesSeniorLead💰 $143,800 - $230,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in timing constraint development, static timing analysis, and synthesis for complex ASIC and SoC designs. Proficient in using industry-standard tools and scripting languages to ensure timing closure and compliance in advanced technology nodes.

Highest-signal resume keywords

Static Timing AnalysisTiming Constraint DevelopmentPrimeTime Tool ProficiencyTcl ScriptingASIC Design Flow Knowledge

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Timing ClosureSynthesisTiming ECO CreationClock Tree SynthesisQuality-of-Results AnalysisStatic AuditsHierarchical Design TimingLow-Power AuditsProcess Corners DefinitionMixed-Signal Block Analysis

Soft Skills

Problem-SolvingAttention to DetailEffective CommunicationTeamworkIndependent Work

Tools & Technologies

PrimeTimeTempusDC-TGenusFishtailVCLPFormalityTclPerlStatic Timing Analysis Tools

Industry Keywords

ASICSoCTiming SignoffAdvanced Technology NodesRTLDesign FlowsClock Tree PlanningHigh-Complexity SiliconTiming ChecksCross Geographical Environment

Tech Stack

Tools & technologies

Perl

About the role

Key responsibilities & impact

Contribute to constraint development, constraint validation, synthesis, CDC audits, RDC audits, static equivalence audits, low-power audits, and timing closure of mission-critical IP and ASIC blocks in advanced technology nodes
Develop and validate timing constraints for intricate SoC designs
Perform static timing analysis using industry-standard tools such as PrimeTime and Tempus
Perform synthesis and run static audits for high-speed, complex digital and mixed-signal blocks
Define and implement timing signoff methodologies, including process corners, derates, and uncertainties
Conduct pre-route timing checks and quality-of-results (QoR) analysis
Automate timing analysis processes using Tcl or Perl
Provide guidance on clock tree synthesis and optimization for energy-efficient designs
Ensure compliance with timing signoff checklists and criteria
Generate timing ECOs for timing closure
Drive timing closure for complex IP and ASIC blocks

Requirements

What you’ll need

Experience with high-complexity silicon in advanced technology nodes
Familiarity with timing constraint development for hierarchical designs
Knowledge of clock tree planning and implementation for SoCs
Experience with timing ECO creation and final timing signoff
Proficiency in STA tools, including PrimeTime, TCM, and Tempus
Proficiency in Tcl or Perl scripting
Proficiency in synthesis and audit tools, including DC-T, Genus, Fishtail, VCLP, and Formality
Strong understanding of ASIC design flows, including RTL and place-and-route
Excellent problem-solving skills and attention to detail
Effective communication and teamwork abilities
Ability to work independently in a fast paced, cross geographical environment
Direct or indirect experience with RTL/Design is a plus
At a minimum, Bachelor's degree and 12+ years of related experience, or Master's degree and 10+ years of related experience, or PhD and 7+ years of related experience
Post-graduate coursework is highly desirable

Benefits

Comp & perks

Discretionary annual bonus
Competitive new hire equity grant
Annual equity awards
Medical, dental and vision plans
401(K) participation including company matching
Employee Stock Purchase Program (ESPP)
Employee Assistance Program (EAP)
Company paid holidays
Paid sick leave and vacation time
Paid Family Leave and other leaves of absence according to applicable laws