Physical Design Engineer

Broadcom

. Work on design implementation activities related to place and route and/or timing closure, including floor-planning, partitioning, placement, clock tree synthesis, route, timing analysis, timing closure and physical verification (LVS/DRC) .

Posted 10/30/2026full-timeUnited StatesSeniorLead💰 $143,800 - $230,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in place and route, timing analysis, and physical verification for ASIC/SoC design, with a strong focus on achieving PPA metrics and implementing ECOs. Proficient in using industry-standard tools and methodologies to ensure right-first-time silicon outcomes.

Highest-signal resume keywords

Place And Route ExpertiseTiming Analysis And ClosurePhysical Verification (LVS/DRC)Experience With Primetime And ICC2Full Chip Tapeout Experience

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Floor-PlanningPartitioningPlacementClock Tree SynthesisRouteTiming AnalysisTiming ClosureECO ImplementationFormal VerificationConstraints Development

Soft Skills

Problem SolvingSelf-StarterExcellent Communication

Tools & Technologies

PrimetimeICC2InnovusCaliberLEC

Industry Keywords

ASIC DesignSoC Design7nm TechnologyPPA MetricsDesign Methodology

About the role

Key responsibilities & impact

Work on design implementation activities related to place and route and/or timing closure, including floor-planning, partitioning, placement, clock tree synthesis, route, timing analysis, timing closure and physical verification (LVS/DRC)
Drive tools and methodologies to achieve desired PPA metrics
Complete equivalence checks, STA, timing closure and power optimization
Implement timing and functional ECOs
Apply Broadcom's proven design methodology and milestone flow to meet criteria for achieving right-first-time silicon

Requirements

What you’ll need

Primary expertise in place and route and/or timing (constraints, STA)
Proficient in design implementation activities at both block and SoC level
Experience in floor-planning, partitioning, placement, clock tree synthesis, route and physical verification and/or constraints development, constraints validation, timing analysis and closure
Experience with formal verification, timing analysis and ECO implementation
Experience with Primetime, ICC2, Innovus, Caliber, LEC, PrimeTime or similar tools highly desirable
Full chip tapeout experience based on 7nm and lower technologies highly preferred
Hands-on experience with timing analysis and place and route tools for ASIC/SoC design
Good problem solver
Self-starter able to work independently
Experience working in a global team and dynamic environment
Ability to learn and adapt to new tools and methodologies
Excellent communication skills
BS in Electrical Engineering, Computer Engineering or related field and 12+ years of related experience; or MS in Electrical Engineering, Computer Engineering or related field and 10+ years of related experience

Benefits

Comp & perks

Discretionary annual bonus
Competitive new hire equity grant
Annual equity awards
Medical, dental and vision plans
401(K) participation including company matching
Employee Stock Purchase Program (ESPP)
Employee Assistance Program (EAP)
Company paid holidays
Paid sick leave and vacation time
Paid Family Leave and other leaves of absence in accordance with applicable laws