Principal Die-to-Die Interconnect Modeling Architect

Broadcom

. Lead a technical team in building and evolving a foundational modeling platform for die-to-die (D2D) PHY designs .

Posted 10/8/2026full-timeUnited StatesLead💰 $167,500 - $268,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in developing and validating behavioral and architectural models for die-to-die communication systems, utilizing advanced tools such as MATLAB, Python, and SystemC. Possesses strong leadership skills in guiding multidisciplinary teams through architectural verification and performance validation processes.

Highest-signal resume keywords

D2D Communication Systems ArchitectureBehavioral And Architectural ModelingArchitectural VerificationHigh-Speed SerDesCommunication Theory

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Algorithm DevelopmentSystem-Level ModelingMonte Carlo EvaluationsStatistical AnalysisPredictive Adaptation AlgorithmsArchitectural Sensitivity AnalysisEqualization AlgorithmsSignal Processing AlgorithmsPerformance Metrics DefinitionSilicon Validation

Soft Skills

Technical LeadershipMentoringCollaborationCommunication

Tools & Technologies

MATLABPythonSystemCVerilog

Industry Keywords

Electrical EngineeringComputer EngineeringAdvanced PackagingSilicon CorrelationDie-To-Die CommunicationUCIe3D Integration

Tech Stack

Tools & technologies

Python

About the role

Key responsibilities & impact

Lead a technical team in building and evolving a foundational modeling platform for die-to-die (D2D) PHY designs
Apply communication theory, develop algorithms, perform system-level modeling, predict performance, model adaptation algorithms, and conduct architectural verification
Perform evaluation and tradeoff analysis using statistical tools across signaling schemes
Analyze hardware architecture and implementation tradeoffs, including equalization, error terms, and noise budgets
Drive algorithm verification of Verilog implementations
Perform predictive adaptation algorithm run-time modeling and Monte Carlo evaluations of adaptation algorithms
Develop behavioral and architectural models predicting complete link behavior before implementation
Build system-level models using MATLAB, Python, SystemC, or equivalent environments
Model transmitter, receiver, package, channel, clocking, equalization, adaptation, and protocol interactions
Predict link performance including BER, latency, throughput, bandwidth density, power consumption, energy efficiency, and manufacturing margin
Perform architectural sensitivity analyses across PVT, aging, package variation, jitter, noise, and channel impairments
Analyze equalization, timing recovery, clock recovery, calibration, and adaptive signal processing algorithms
Guide algorithm development from mathematical concepts through production silicon implementation
Establish timing and operating margins and collaborate with implementation teams to ensure assumptions are achievable in silicon
Define architectural verification strategies, performance metrics, methodologies, and success criteria
Develop behavioral reference models as golden standards for RTL implementation, verification, software development, and silicon validation
Correlate behavioral models, RTL simulation, laboratory characterization, and production silicon
Validate architectural assumptions through simulation and silicon measurements, identify performance gaps, and drive corrective actions
Develop validation strategies covering nominal operation, corner cases, interoperability, and robustness
Provide technical leadership across architecture, analog, digital, firmware, packaging, signal integrity, verification, validation, and product engineering organizations
Lead architecture reviews and critical technical decision-making throughout the product lifecycle
Mentor engineers and architects in communication systems, modeling, and architecture development
Influence technology roadmaps and drive innovation in next-generation die-to-die communication systems

Requirements

What you’ll need

MS in Electrical Engineering, Computer Engineering, and 15 or more years in related field experience; or PhD in Electrical Engineering, Computer Engineering, and 12 or more years in related field experience
Deep understanding of communication theory, equalization, and adaptive algorithms
Experience in high-speed SerDes, or D2D communication systems architecture
Extensive experience developing behavioral and architectural models using MATLAB, Python, SystemC, or equivalent tools
Experience with architecture model to RTL to verification
Experience leading architectural verification, silicon correlation, and performance validation across multidisciplinary engineering teams
Desired: Demonstrated expertise in D2D, UCIe, or other short-reach die-to-die communication
Desired: Expertise in advanced packaging including silicon interposers, EMIB, hybrid bonding, and 3D integration
Desired: Management experience

Benefits

Comp & perks

Discretionary annual bonus
Competitive new hire equity grant
Annual equity awards
Medical plans
Dental plans
Vision plans
401(K) participation including company matching
Employee Stock Purchase Program (ESPP)
Employee Assistance Program (EAP)
Company paid holidays
Paid sick leave
Vacation time
Paid Family Leave and other leaves of absence in accordance with applicable laws