Staff IC Verification Engineer

Broadcom

. Develop verification environments using modern verification techniques, including SystemVerilog and UVM .

Posted 11/2/2026full-timeUnited StatesLead💰 $109,700 - $175,500 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Expertise in developing verification environments using SystemVerilog and UVM, with a strong focus on designing verification classes and implementing coverage and assertions. Proven ability to analyze and debug simulation failures while contributing effectively to SoC and IP development programs.

Highest-signal resume keywords

SystemVerilog ExpertiseUVM Design ExperienceHDL Languages ProficiencyOOP Techniques FamiliarityCritical Thinking Skills

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

SystemVerilogUVMVerilogVHDLHDL SimulatorsOOP LanguagesC++JavaCoverage AnalysisTest Case Development

Soft Skills

Excellent CommunicationInterpersonal SkillsLeadership SkillsCritical ThinkingIndependent Problem Solving

Industry Keywords

SoC DevelopmentIP DevelopmentAI ChipsStorage ChipsMatrix Organization

Tech Stack

Tools & technologies

JavaC++

About the role

Key responsibilities & impact

Develop verification environments using modern verification techniques, including SystemVerilog and UVM
Design verification classes such as UVM sequences, agents, scoreboards, and behavioral models
Implement coverage and assertions using SystemVerilog
Develop random and directed test cases to close coverage
Analyze and debug simulation failures
Analyze coverage results
Contribute as a highly productive individual contributor to system- and sub-block-level verification
Work on SoC and IP development programs for AI and storage chips
Support subsystem development to meet customer requirements

Requirements

What you’ll need

Bachelor's degree in EE, CE, or CS and 8+ years of related experience; or Master's degree in EE, CE, or CS and 6+ years of related experience
Excellent communication and interpersonal skills
Experience communicating in a matrix organization to achieve common goals
Demonstrated expertise in HDL languages Verilog/VHDL and SystemVerilog
Experience designing in constrained random environments using UVM, OVM, or VMM
Experience running and debugging using HDL simulators
Demonstrated familiarity with OOP languages (C++, Java, etc.) and proficiency with OOP techniques
Demonstrated critical thinking to conceive and develop innovative solutions to solve complex engineering problems
Demonstrated leadership skills
Ability to act independently to determine methods and procedures on new or special assignments
Must have legal authorization to work in the US
This position does not have funding to support company-sponsored immigration support

Benefits

Comp & perks

Discretionary annual bonus
Competitive new hire equity grant
Annual equity awards
Medical plans
Dental plans
Vision plans
401(K) participation including company matching
Employee Stock Purchase Program (ESPP)
Employee Assistance Program (EAP)
Company paid holidays
Paid sick leave
Vacation time
Paid Family Leave and other leaves of absence according to applicable laws