VLSI ASIC Verification Engineer

Broadcom

. Own functional verification of complex digital blocks and subsystems .

Posted 11/11/2026full-timeUnited StatesSeniorLead💰 $109,700 - $175,500 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Expertise in functional verification of complex digital blocks and subsystems, with a strong focus on SystemVerilog and UVM methodologies. Proven ability to develop comprehensive verification plans, drive functional coverage, and utilize industry-standard simulation tools for effective debugging and validation.

Highest-signal resume keywords

SystemVerilog ProficiencyUVM Architecture ExpertiseConstrained-Random VerificationFunctional Coverage ClosureScripting Skills in Python

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Functional VerificationVerification PlansTestbench DevelopmentSystemVerilog AssertionsDebugging WaveformsRegression ManagementAssertion-Based VerificationMicro-Architectural AnalysisSimulation ToolsMemory Hierarchies

Tools & Technologies

Synopsys VCSCadence XceliumMentor QuestaVerdiPythonPerlTcl

Industry Keywords

ASIC Design VerificationSoC VerificationIP Design VerificationAMBA ProtocolsRISC-V ArchitectureARM ArchitectureX86 ArchitectureHigh-Speed InterfacesCache Coherency ProtocolsVirtual Memory Management

Tech Stack

Tools & technologies

PerlPython

About the role

Key responsibilities & impact

Own functional verification of complex digital blocks and subsystems
Analyze micro-architectural specifications to create comprehensive verification plans, trace requirements, and identify edge and corner cases
Design and build modular, reusable verification environments and testbenches using SystemVerilog and UVM
Develop constrained-random stimulus, functional coverage models, scoreboards, and reference models
Write SystemVerilog Assertions to catch design violations early
Run simulations, debug waveforms, and root-cause RTL-to-testbench mismatches
Drive functional and code coverage to 100% closure prior to tape-out
Maintain automated regression suites using Python, Perl, or Tcl
Join the silicon engineering team and ensure zero-bug tape-outs

Requirements

What you’ll need

B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field
Minimum 8 years of hands-on experience in ASIC, SoC, or IP design verification
Deep proficiency in SystemVerilog and UVM architectures, including agents, drivers, monitors, scoreboards, and virtual sequences
Solid working knowledge of AMBA protocols, including AXI, AHB, and APB, and memory/DMA controllers
Proven track record in constrained-random verification, functional coverage closure, and assertion-based verification using SVA
Hands-on experience with industry-standard simulation and debug tools, such as Synopsys VCS, Cadence Xcelium/Incisive, Mentor/Siemens Questa, or Verdi
Strong scripting skills in Python, Tcl, or Perl for build-flow automation and regression management
Familiarity with formal verification tools and techniques
Hands-on verification experience with RISC-V, ARM, or x86 core or subsystem architectures
Deep understanding of processor pipelines, branch prediction, out-of-order execution, superscalar designs, and execution units such as ALU/FPU
Familiarity with complex memory hierarchies, including L1/L2 caches, cache coherency protocols, MMUs, and virtual memory management
Exposure to high-speed interfaces or external protocols such as DDR, PCIe, NVMe, SATA, or SAS

Benefits

Comp & perks

Discretionary annual bonus
Competitive new hire equity grant
Annual equity awards
Medical plans
Dental plans
Vision plans
401(K) participation including company matching
Employee Stock Purchase Program (ESPP)
Employee Assistance Program (EAP)
Company paid holidays
Paid sick leave
Vacation time
Paid Family Leave and other leaves of absence in accordance with applicable laws