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Capgemini

RF Analog Layout Engineer

Capgemini

. Design layouts for high-frequency analog/RF blocks in FinFET technology .

Posted 10/2/2026full-timeRemote • UkraineMid-LevelSeniorWebsite

Core Competencies

Role fit
Core Competencies

Use this summary to align your resume positioning with the role.

Expertise in RF layout design for high-frequency analog/RF blocks, with a strong focus on minimizing parasitic effects and ensuring compliance with advanced design rules. Proficient in collaborating with RF designers to achieve performance targets while utilizing RF-aware EDA tools for layout automation and verification.

Highest-signal resume keywords
RF Layout DesignParasitic ControlRF-Aware EDA ToolsEM ModelingScripting for Layout Automation

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills
RF Circuit DesignLayout OptimizationMatching TechniquesHigh-Frequency Signal RoutingEM/IR ReliabilityPost-Layout SimulationRF Sign-Off FlowsDifferential Pair DesignCoaxial ShieldingGround Shielding
Tools & Technologies
EDA ToolsEM Extraction ToolsPost-Layout Simulation Flows
Industry Keywords
FinFET TechnologyHigh-Frequency CircuitsCrosstalk ReductionColor-Aware RoutingMulti-Patterning Constraints

About the role

Key responsibilities & impact
  • Design layouts for high-frequency analog/RF blocks in FinFET technology
  • Design layouts for RF circuits such as LNAs, mixers, VCOs, and PLL sub-blocks
  • Optimize routing for high-frequency signals by minimizing parasitic capacitance and inductance
  • Implement coaxial, differential, and ground shielding strategies to reduce coupling and crosstalk
  • Address EM/IR reliability for high-current RF paths and comply with advanced DRC/LVS rules
  • Apply matching techniques for RF differential pairs and passive components including inductors and capacitors
  • Collaborate with RF designers to meet gain, noise figure, and phase noise targets
  • Ensure compliance with color-aware routing and multi-patterning constraints for RF metal layers

Requirements

What you’ll need
  • Hands-on experience in RF layout design at FinFET nodes
  • Deep understanding of parasitic control for high-frequency circuits
  • Familiarity with EM modeling, substrate coupling, and isolation techniques
  • Proficiency in RF-aware EDA tools and post-layout simulation flows
  • Knowledge of reliability and aging effects in RF devices and mitigation strategies
  • Experience with RF sign-off flows and EM extraction tools (preferred)
  • Ability to optimize layout for low phase noise and high linearity (preferred)
  • Scripting skills for RF layout automation and verification (preferred)

Benefits

Comp & perks
  • Health insurance from the first days, regardless of the probationary period
  • Christmas holidays from 25 December to 31 December
  • Cooperation with Superhumans center and Veteran HUB
  • Psychological counseling provided by the Veteran Hub
  • Internal policy making the company friendly to military and veterans