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Core Competencies
Role fitCore Competencies
Use this summary to align your resume positioning with the role.
Expertise in IP design with a strong focus on Verilog implementation, debugging, and compliance with Ethernet protocols and IEEE standards. Proven ability to collaborate effectively with cross-functional teams to deliver high-quality design solutions.
Highest-signal resume keywords
IP DesignVerilog ImplementationDebugging FirmwareEthernet Protocols KnowledgeSystemVerilog Proficiency
ATS Keywords
Tailor your resumeApplicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard Skills
VerilogDebugging FirmwareRTL Code DebuggingTiming ClosureAXI StreamingAXI4-LiteScripting with PerlScripting with PythonASIC Flow ToolsCode Coverage
Soft Skills
Interpersonal SkillsWritten CommunicationProblem-Solving SkillsOrganizational SkillsExecution Skills
Tools & Technologies
PrimetimeDesign CompilerSimulation Tools
Industry Keywords
IEEE 802.3 StandardsMAC/PCS/PMAPTP (IEEE 1588)Pause/Flow ControlFEC10GE to 100GE
Tech Stack
Tools & technologiesPerlPython
About the role
Key responsibilities & impact- Understand design requirements, microarchitecture, and systems architecture of the team's IP and systems solutions
- Collaborate with design and verification engineers to understand features and support requirements
- Implement key functional blocks compliant with design and architecture specifications using Verilog
- Debug test failures to determine root cause
- Work with verification and emulation engineers to resolve design defects and correct design issues
Requirements
What you’ll need- B.E/M.E/M.Tech or B.S/M.S in EE/ECE with 10+ years of relevant experience in IP design
- Knowledge of Ethernet protocols and IEEE 802.3 standards, including MAC/PCS/PMA, PTP (IEEE 1588), pause/flow control, and FEC for speeds from 10GE up to 100GE and beyond
- Domain knowledge of AXI streaming, AXI4-Lite, and other connectivity protocols
- Experience in closing timing of complex designs
- Proficient in debugging firmware and RTL code using simulation tools
- Knowledge of ASIC flow tools such as Primetime and Design Compiler, code coverage, and LINT is an added advantage
- Good working knowledge of SystemVerilog
- Scripting language experience with Perl and Python
- Self-driven, motivated, and result-oriented
- Excellent interpersonal, written, group communication, and problem-solving skills
- Good organizational and execution skills, ability to multitask, prioritize, and meet deadlines with high-quality deliverables
Benefits
Comp & perks- Health insurance from the first days, regardless of the probationary period
- Christmas holidays from December 25 to December 31
- Psychological counseling provided by the Veteran Hub
- Cooperation with Superhumans center and Veteran HUB
- Internal policy making the company friendly to military and veterans