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Core Competencies
Role fitCore Competencies
Use this summary to align your resume positioning with the role.
Demonstrates expertise in custom analog and mixed-signal IC layout, including ownership of complex layouts and successful tapeouts. Proficient in physical verification, layout automation, and mentoring junior engineers while collaborating with cross-functional teams.
Highest-signal resume keywords
Custom Analog IC Layout ExperienceCadence Virtuoso ProficiencyPhysical Verification ExpertiseMentoring Junior EngineersDeep-Submicron CMOS Knowledge
ATS Keywords
Tailor your resumeApplicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard Skills
Custom Analog IC LayoutMixed-Signal IC LayoutTapeout OwnershipDevice MatchingParasitic ResistanceHigh-Speed AmplifiersFinFET LayoutPERC-Based ESD DebuggingLayout AutomationHigh-Frequency Routing
Soft Skills
Independent Decision-MakingProject DeliveryProblem-SolvingCommunication
Tools & Technologies
Cadence VirtuosoSiemens CalibreAnsys TotemAI-Assisted Coding Tools
Industry Keywords
Electrical EngineeringDeep-Submicron CMOS ProcessesEM/IR ToolsHigh-Speed SerDesPrecision Analog Circuits
Tech Stack
Tools & technologiesNode.js
About the role
Key responsibilities & impact- Own assigned layout projects from feasibility and floorplanning through implementation, physical verification, integration, and tapeout readiness
- Define project scope, implementation plans, effort estimates, milestones, and review checkpoints
- Coordinate contributors, track dependencies, and resolve implementation bottlenecks
- Lead layout reviews and quality checks with layout teams and circuit designers
- Establish implementation constraints and evaluate performance, area, device matching, parasitics, isolation, and reliability tradeoffs
- Develop layout strategies for performance-critical circuits and high-speed signal paths
- Review extracted parasitics and implement targeted improvements
- Drive physical-verification and reliability closure, including DRC, LVS, ERC, antenna, BUMP, EM/IR, and PERC checks
- Mentor junior engineers through hands-on problem-solving and design feedback
- Partner with CAD and AI/ML engineers on environment setup, tool evaluation, automation, reusable layout structures, RFIC and analog layout generation, PCell development, and design space exploration
- Communicate progress, risks, and corrective actions against milestones
Requirements
What you’ll need- Bachelor's degree or higher in Electrical Engineering, or a related field
- 5+ years of custom analog or mixed-signal IC layout experience
- Ownership of complex layouts through successful tapeouts
- Independent technical decision-making and project delivery experience
- Experience guiding layout contributors and hands-on implementation
- Experience with ADCs, DACs, SerDes, PLLs, high-speed amplifiers, or precision analog circuits
- Proficiency with Cadence Virtuoso and Siemens Calibre, or comparable custom-layout and physical-verification tools
- Knowledge of device matching, parasitic resistance and capacitance, coupling, high-frequency routing, shielding, ESD-aware layout, electromigration, and IR drop
- Knowledge of deep-submicron CMOS processes, foundry design rules, device isolation, and layout-dependent effects
- Practical experience with FinFET layout and advanced-node implementation
- Experience in high-speed SerDes or data converters
- Experience with Ansys Totem or comparable EM/IR tools and PERC-based ESD and reliability debugging
- Deep knowledge of noise isolation and shielding
- PCell development and layout automation skills
- Experience using AI-assisted coding tools for layout-flow scripts, automation, and engineering utilities
Benefits
Comp & perks- Development opportunities
- Flexible work arrangements
- Medical, dental, and vision plans
- DCPP (Canada) with company matching
- Employee Stock Purchase Program (ESPP)
- Employee Assistance Program (EAP)
- Company-paid holidays
- Paid sick leave
- Vacation time
- Paid Family Leave and other leaves of absence
