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Design Verification Engineer Internship
Cirrus Logic. Support functional verification of mixed-signal products .
Core Competencies
Role fitCore Competencies
Use this summary to align your resume positioning with the role.
Demonstrates expertise in Hardware Description Languages (HDLs) such as Verilog and VHDL, along with familiarity in Hardware Verification Languages (HVLs) like SystemVerilog/UVM. Strong understanding of digital design fundamentals and verification methodologies is essential for supporting functional verification of mixed-signal products.
Highest-signal resume keywords
Hardware Description Languages (HDLs)Hardware Verification Languages (HVLs)Digital Design FundamentalsVerification MethodologiesMixed-Signal Modeling
ATS Keywords
Tailor your resumeApplicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard Skills
VerilogVHDLSystemVerilogUVMDigital DesignVerification PlanningTestbench CreationFailure AnalysisDebuggingTest Generation
Industry Keywords
Mixed-Signal ProductsPre-Silicon VerificationPost-Silicon ValidationCoverage AnalysisVerification Flow Development
About the role
Key responsibilities & impact- Support functional verification of mixed-signal products
- Work closely with digital and analog designers, applications engineers, and manufacturing test teams
- Ensure robust product performance through pre-silicon verification and post-silicon validation
- Assist in verification planning and strategy development
- Support testbench creation, maintenance, and enhancement
- Contribute to failure analysis, debugging, and resolution efforts
- Help with coverage analysis and population
- Work on digital/mixed-signal modeling
- Develop directed and constraint-random test generation
- Contribute to verification flow development
Requirements
What you’ll need- Currently pursuing an MS or PhD in Electrical Engineering or a related field
- Strong background in Hardware Description Languages (HDLs) such as Verilog or VHDL
- Familiarity with Hardware Verification Languages (HVLs) like SystemVerilog/UVM, Vera, or e
- Solid understanding of digital design fundamentals and verification methodologies
- Interns must be based within commutable distance of the work location or willing to relocate before beginning the internship
- Candidates must be able to access technical data without requiring an export license
- Cirrus Logic is unable to sponsor or obtain export licenses for this role
Benefits
Comp & perks- Full-time internship schedule
- Inclusion and fairness-focused culture
- Meaningful community engagement
- Enjoyable employee experiences
- Opportunity to grow your career