Intern - Formal Verification Engineer

Cirrus Logic

. Support the formal verification team in following and improving defined methodology practices .

Posted 10/27/2026internshipAustin • Texas • United StatesEntry LevelWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in formal verification methodologies and the development of test plans for microarchitecture and design. Proficient in SystemVerilog and familiar with scripting languages, with a strong foundation in digital design principles.

Highest-signal resume keywords

Formal Verification MethodologiesSystemVerilog ProficiencyUVM MethodologiesScripting LanguagesProperty-Based Model-Checking

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Formal VerificationTest Plan DevelopmentFailure AnalysisCoverage AnalysisVerification Environment DesignDigital Design FundamentalsSignal ProcessingProperty LanguagesModel-CheckingMicroarchitecture Verification

Soft Skills

Excellent Communication SkillsCollaborative Approach

Tools & Technologies

SystemVerilogPythonPerlTCLBash

Industry Keywords

Electrical EngineeringComputer EngineeringDigital DesignFormal Property LanguagesUVM

Tech Stack

Tools & technologies

PerlPython

About the role

Key responsibilities & impact

Support the formal verification team in following and improving defined methodology practices
Develop test plans and verification methodologies to formally verify microarchitecture and design
Perform failure analysis and resolution, coverage analysis, and population
Implement and improve functional and formal verification
Apply formal verification to digital designs

Requirements

What you’ll need

Currently enrolled in a Master’s or PhD program in Electrical and Computer Engineering
Available for full-time employment during the internship
Must be based within commutable distance of the Austin, Texas work location or willing to relocate before the internship
Must be able to access technical data without requiring an export license
Knowledge of designing and implementing verification environments for module-level designs
Proficiency in SystemVerilog
Familiarity with scripting languages such as Python, Perl, TCL, and Bash
Experience or knowledge in UVM or equivalent methodologies
Knowledge of formal property languages such as SVA
Knowledge of property-based model-checking
Knowledge of signal processing and analog or digital design fundamentals
Excellent communication skills and collaborative approach

Benefits

Comp & perks

In-office work schedule of 2+ days per week; interns may work in the office up to 5 days per week based on business needs and team preference
Relocation opportunity/requirement prior to beginning the internship if not within commuting distance
Inclusive and fair workplace culture
Meaningful community engagement
Enjoyable employee experiences