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Core Competencies
Role fitCore Competencies
Use this summary to align your resume positioning with the role.
Demonstrates expertise in IP- and system-level verification using SystemVerilog and UVM, with a strong focus on developing functional coverage models and SystemVerilog Assertions (SVA). Proven ability to collaborate with multidisciplinary teams to drive verification closure and manage verification metrics effectively.
Highest-signal resume keywords
SystemVerilog VerificationUVM MethodologyFunctional Coverage DevelopmentFPGA-Based ValidationCoding in Python, C++, or Rust
ATS Keywords
Tailor your resumeApplicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard Skills
IP-Level VerificationSystem-Level VerificationConstrained-Random TestingSimulation TechniquesGate-Level VerificationFormal Verification TechniquesDebugging Hardware/Software InteractionsVerification PlanningCoverage Metrics AnalysisLinux Scripting
Soft Skills
CollaborationOwnership of DeliverablesProblem-Solving
Tools & Technologies
GitSVNGitLabJenkins
Industry Keywords
AMBA AXIAHBAPBFPGA PrototypingSecure Systems
Tech Stack
Tools & technologiesJenkinsLinuxPythonRustSubversionC++
About the role
Key responsibilities & impact- Define comprehensive verification strategies, plans, test scenarios, and coverage goals from architectural specifications
- Review technical requirements from a verification perspective
- Develop and maintain scalable, reusable IP- and system-level verification environments using SystemVerilog/UVM
- Build stimulus generators, checkers, and formal verification setups
- Run simulations and perform root-cause failure analysis
- Support FPGA-based validation
- Drive verification closure by resolving coverage gaps and residual risks
- Develop functional coverage models and SystemVerilog Assertions (SVA)
- Maintain automated verification flows for regression and testing pipelines
- Partner with hardware designers and software engineers
- Own estimation, prioritization, and regular reporting on verification metrics, progress, and risks
- Support verification of new Codasip IP for secure systems and develop system-level testbenches for ASIC implementation and FPGA prototyping
Requirements
What you’ll need- Candidates must be currently located in and have working rights in the UK
- Solid hands-on experience in IP- and system-level verification using SystemVerilog and UVM, including constrained-random testing, simulation, and gate-level verification
- Proven ability to build verification plans, develop functional coverage and SystemVerilog Assertions (SVA), analyze coverage metrics toward closure, and apply formal verification techniques
- Strong coding skills in SystemVerilog, Python, C++, or Rust
- Linux scripting and workflow automation experience
- Familiarity with Git or SVN and continuous integration tools such as GitLab or Jenkins
- Solid grasp of computer systems and processor architecture
- Ability to debug complex hardware/software interactions across multidisciplinary teams
- Demonstrated ownership of verification deliverables from initial planning through implementation to final sign-off
- Knowledge of AMBA AXI, AHB, or APB is desirable
- Experience with FPGA-based prototyping or validation is desirable