Senior ASIC Design Engineer

Cornelis Networks

. Implement RTL designs using Verilog/SystemVerilog for high-speed data paths and packet processing logic .

Posted 9/18/2026full-timeRemote • California • United StatesSeniorWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in RTL design using Verilog and SystemVerilog, with a strong focus on high-speed data paths and packet processing. Proven ability to collaborate across teams for system-level debugging and optimization in ASIC development.

Highest-signal resume keywords

RTL Design Using VerilogSystem-Level DebugHigh-Speed Data PathsTiming ClosureScripting Languages (TCL, Python, Perl)

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

VerilogSystemVerilogDigital DesignPacket ProcessingTiming ClosureRoot Cause AnalysisMultiple Clock Domain DesignsAsynchronous InterfacesPerformance OptimizationPower-Aware Design

Soft Skills

Strong Verbal CommunicationStrong Written Communication

Tools & Technologies

Design CompilerSpyglassPrimeTime

Industry Keywords

Host Ethernet Adaptor ArchitecturesNetworking ProtocolsASIC DevelopmentPost-Silicon ValidationHost Fabric Interface

Tech Stack

Tools & technologies

PerlPython

About the role

Key responsibilities & impact

Implement RTL designs using Verilog/SystemVerilog for high-speed data paths and packet processing logic
Collaborate with verification engineers to create block- and system-level test plans
Define timing constraints for RTL blocks and work with Physical Design engineers to optimize timing closure
Support post-silicon validation with hardware, firmware, and software teams to debug and resolve ASIC issues
Contribute to performance optimization and power-aware design strategies for Host Fabric Interface subsystems
Develop world-class SoCs for high-performance computing, advanced data analytics, and AI interconnect solutions

Requirements

What you’ll need

B.S. or M.S. degree in Computer Engineering, Electrical Engineering, or related field
8+ years of post-college experience in digital design
Proficiency in Verilog and SystemVerilog
Experience in RTL design for high-speed data paths or packet processing in ASICs
Deep understanding of Host Ethernet adaptor architectures
Familiarity with timing closure and modern physical design methodologies
Proven ability in system-level debug and root cause analysis of technical issues
Strong verbal and written communication skills
Knowledge of Ethernet architecture and networking protocols
Prior experience with RTL development for Ethernet host adapters and system debug
Expertise in multiple clock domain designs and asynchronous interfaces
5+ years of experience with scripting languages such as TCL, Python, or Perl
Familiarity with EDA tools like Design Compiler, Spyglass, or PrimeTime

Benefits

Comp & perks

Equity, cash, and incentives
Health, medical, dental, and vision coverage
Disability and life insurance
Dependent care flexible spending account
Accidental injury insurance
Pet insurance
Generous paid holidays
401(k) with company match
Open Time Off (OTO) for regular full-time exempt employees
Sick time
Bonding leave
Pregnancy disability leave
Flexible work environment