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Cornelis Networks

Senior Verification Design Automation Engineer

Cornelis Networks

. Develop, maintain, and improve AI-based flows for verification infrastructure, automation frameworks, and execution environments across block, subsystem, and SoC-level ASIC verification .

Posted 9/18/2026full-timeRemote • United StatesSeniorWebsite

Core Competencies

Role fit
Core Competencies

Use this summary to align your resume positioning with the role.

Demonstrates extensive experience in AI-based verification infrastructure and automation frameworks, with strong capabilities in scripting and automation using Python, Perl, and Tcl. Proficient in managing complex verification environments and driving improvements in reliability and efficiency.

Highest-signal resume keywords
AI-Based Verification InfrastructureScripting and Automation (Python, Perl, Tcl)Linux-Based Engineering EnvironmentsSystemVerilog/UVM Verification MethodologiesEDA Tool Integration

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills
PythonPerlTclShell ScriptingMakeAutomation TechnologiesDebugging Automation FailuresRegression ExecutionEDA Tool FlowsData Analytics
Soft Skills
CollaborationProblem-Solving
Tools & Technologies
GitHub ActionsGit WorkflowsJob SchedulersContinuous Integration FlowsReporting Utilities
Industry Keywords
ASIC VerificationDesign AutomationVerification AutomationDistributed Compute InfrastructureVerification Execution

Tech Stack

Tools & technologies
LinuxPerlPythonShell Scripting

About the role

Key responsibilities & impact
  • Develop, maintain, and improve AI-based flows for verification infrastructure, automation frameworks, and execution environments across block, subsystem, and SoC-level ASIC verification
  • Build and support scalable regression flows, dashboards, reporting utilities, and triage automation
  • Create and enhance scripts, tools, and integrations using Python, Perl, Tcl, shell scripting, Make, and related automation technologies
  • Support simulation, coverage, lint, formal, emulation, and continuous integration flows
  • Collaborate with verification, design, architecture, and CAD teams
  • Manage compute, storage, license, queue, and job-dispatch infrastructure issues affecting verification execution and turnaround time
  • Drive automation improvements to make verification environments more reliable, reproducible, debuggable, and efficient across geographically distributed teams

Requirements

What you’ll need
  • 8+ years of post-college experience in design automation, verification automation, CAD, infrastructure, or ASIC verification support
  • 8+ years of experience with scripting and automation using Python, Perl, Tcl, shell scripting, or similar languages
  • Experience supporting Linux-based engineering environments, source-control systems, build flows, regression execution, and EDA tool integration
  • Ability to debug automation failures, tool/runtime issues, infrastructure bottlenecks, and workflow inefficiencies in complex verification environments
  • B.S. Degree in Computer Engineering, Computer Science, Electrical Engineering, or a related technical discipline
  • Experience supporting large-scale ASIC verification environments, regression farms, EDA tool flows, and distributed compute infrastructure
  • Knowledge of SystemVerilog/UVM verification methodologies
  • Experience with GitHub Actions, Git workflows, job schedulers, data analytics, and automation for regression management, coverage tracking, and productivity metrics
  • Employees must reside within the United States

Benefits

Comp & perks
  • Equity, cash, and incentives
  • Health benefits
  • Retirement benefits
  • Medical coverage
  • Dental coverage
  • Vision coverage
  • Disability insurance
  • Life insurance
  • Dependent care flexible spending account
  • Accidental injury insurance
  • Pet insurance
  • Generous paid holidays
  • 401(k) with company match
  • Open Time Off (OTO) for regular full-time exempt employees
  • Sick time
  • Bonding leave
  • Pregnancy disability leave
  • Flexible work environment