Architect

Delos Data

. Define, architect, and guide the development of next-generation, high-performance ASICs .

Posted 10/30/2026full-timePalo Alto • California • United StatesSeniorLead💰 $160,000 - $280,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Expertise in ASIC architecture and micro-architecture, with a strong focus on high-performance silicon design and power management strategies. Proficient in performance modeling and analysis, utilizing tools such as SystemC, C++, and Python to validate architectural assumptions.

Highest-signal resume keywords

ASIC ArchitectureSystemVerilog/VerilogPerformance ModelingAI/ML Accelerator DesignLeadership and Mentorship

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

ASIC ArchitectureMicro-ArchitectureSystemCC++PythonPerformance ModelingPower Management StrategiesHigh-Speed Interconnect FabricDesign SpecificationsAutomation Scripting

Soft Skills

Excellent CommunicationProactive Problem SolverLeadershipMentorship

Tools & Technologies

EDA ToolsSynopsys Design CompilerCadence GenusPre-Silicon Emulation Platforms

Industry Keywords

AI AcceleratorsNetworking SiliconHigh-Performance ComputingCPU/GPU CoresMemory HierarchiesEthernetPCIeUAL

Tech Stack

Tools & technologies

PerlPythonC++

About the role

Key responsibilities & impact

Define, architect, and guide the development of next-generation, high-performance ASICs
Translate high-level system requirements into detailed architectural specifications
Define architecture for IP blocks, sub-systems, and full SoC integration for advanced AI accelerators, networking, and datacenter computing workloads
Lead creation of Architectural Design Specifications and Micro-architecture Specifications for complex ASICs, including high-speed interconnect fabric and IO protocols
Develop high-level performance models using SystemC/TLM, C++, or Python to analyze workload behaviors and validate architectural assumptions
Optimize chip-level and block-level architecture to meet power, performance, and area goals
Partner with RTL design, verification, physical design, firmware, and software teams
Drive architectural trade-off studies and lead design reviews
Define power management strategies including DVFS, power domains, and clock gating
Mentor junior engineers and contribute to technical leadership

Requirements

What you’ll need

Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science
7+ years of experience in ASIC architecture, micro-architecture, or high-level design
Strong proficiency in SystemVerilog/Verilog and C/C++ or SystemC for modeling
Deep knowledge of computer architecture, including CPU/GPU cores, caches, fabric, and memory hierarchies
Experience with industry-standard protocols such as Ethernet, PCIe or UAL
Familiarity with EDA tools such as Synopsys Design Compiler, Cadence Genus, or similar
Experience with performance modeling and analysis tools
Experience designing AI/ML accelerators or high-performance networking silicon
Proven record of shipping high-performance silicon from concept to tape-out
Familiarity with pre-silicon emulation platforms
Strong scripting skills (Python, Tcl, Perl) for automation
Excellent communication skills and ability to articulate complex architectural concepts
Proactive problem solver capable of working with minimal oversight
Strong leadership and mentorship capabilities

Benefits

Comp & perks

Meaningful equity
Benefits
401k