DFT Engineer

Delos Data

. Develop, implement, and maintain RTL verification environments using UVM or equivalent methodologies .

Posted 9/23/2026full-timeRemote • United StatesMid-LevelSenior💰 $160,000 - $230,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in RTL verification environments using UVM and SystemVerilog, with a strong focus on coverage-driven verification and automation through Python scripting. Proven ability to analyze complex design issues and collaborate effectively with cross-functional teams to ensure high-quality verification outcomes.

Highest-signal resume keywords

RTL VerificationUVM MethodologiesSystemVerilog ProficiencyPython ScriptingDFT Verification

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Digital Design VerificationCoverage-Driven VerificationTestMaxTessentSynopsys VCSSiemens/Mentor QuestaCadence XceliumATPG Patterns VerificationRoot-Cause AnalysisHigh-Speed PHY Logic Verification

Soft Skills

Analytical SkillsProblem-Solving SkillsClear CommunicationAttention to DetailIndependent Task Management

Tools & Technologies

EDA DFT ToolsRegression Testing AutomationChange Control SystemsGit

Industry Keywords

Electrical EngineeringComputer EngineeringSoC-Level DesignsPCIeEthernet

Tech Stack

Tools & technologies

Python

About the role

Key responsibilities & impact

Develop, implement, and maintain RTL verification environments using UVM or equivalent methodologies
Create and execute coverage-driven verification plans aligned with design specifications
Use EDA DFT tools such as TestMax and Tessent to create and run pre-silicon test cases for MBIST and scan fabric
Develop directed test cases for non-vendor-supplied DFT logic
Assist in verifying ATPG patterns, especially at SoC level, and manufacturing reset sequences
Analyze simulation results, debug complex verification and design issues, and perform root-cause analysis with DFT design engineers
Implement and track functional and code coverage, driving verification to closure
Develop reusable verification components and write SystemVerilog Assertions
Participate in design and verification reviews, contributing to testability, correctness, and optimization
Automate regression testing and enhance verification infrastructure using Python and scripting
Contribute to continuous improvement of verification processes, tools, and methodologies
Support post-silicon test bring-up debug with DFT designers

Requirements

What you’ll need

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
5+ years of experience in digital design verification, with at least 2 in DFT verification specifically
Strong hands-on experience with UVM-based or similar verification methodologies
Proficiency in SystemVerilog
Experience in scripting, preferably Python, and automation
Experience with Synopsys VCS, Siemens/Mentor Questa, or Cadence Xcelium
Experience with Synopsys TestMax + Yield Accelerator or Siemens Tessent
Solid understanding of digital design fundamentals
Experience verifying test sequences for high-speed PHY logic including PCIe and Ethernet (10G/40G/100G)
Strong analytical and problem-solving skills
Clear written and verbal communication skills for cross-functional collaboration
High attention to detail and ability to deliver reliable, high-quality verification outcomes
Ability to work independently and manage tasks to completion
Experience with change control systems, especially git
Experience verifying SoC-level designs

Benefits

Comp & perks

Meaningful equity
Benefits
401(k)