Principal Package Engineer

Delos Data

. Architect and deliver advanced multi-die IC packages for high-performance AI accelerators .

Posted 10/1/2026full-timePalo Alto • California • United StatesLead💰 $180,000 - $270,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

Use this summary to align your resume positioning with the role.

Expertise in multi-die IC package design, including substrate materials, stack-ups, and mechanical constraints, with a strong focus on high-performance AI accelerators. Proven ability to manage subcontractors and collaborate with teams on system-level needs and advanced packaging technologies.

Highest-signal resume keywords

Multi-Die Package DesignUCIe IntegrationSubstrate Materials KnowledgeSI/PI CollaborationTSMC/OSAT Interface Experience

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Electrical EngineeringPackage Specifications DefinitionHigh-Speed Signal RoutingPower Distribution Network DesignBump Map DesignBall Map DesignMechanical Constraints DefinitionThermal Behavior AnalysisEmerging Packaging Technologies EvaluationFailure Analysis

Soft Skills

Project ManagementCollaborationCommunication

Tools & Technologies

HFSSSigrity

Industry Keywords

Advanced PackagingAI AcceleratorsSubcontractor ManagementPackage ModelingManufacturability

About the role

Key responsibilities & impact

Architect and deliver advanced multi-die IC packages for high-performance AI accelerators
Select and design optimal multi-die package types, balancing electrical performance, thermal behavior, cost, and manufacturability
Define package specifications, bump map, ball map, interposer requirements, and mechanical constraints
Define substrate stack-ups, bump pitch, ball pitch, routing, via structures, and material choices
Perform high-speed signal escaping, routing, and power distribution network design
Manage subcontractors and work directly with TSMC and/or OSAT on bumping, substrate options, and advanced packaging flows
Partner with IC design, physical design, SI/PI, and board teams to meet system-level needs
Evaluate emerging packaging technologies and drive adoption for next-generation products
Support package-level bring-up, failure analysis, debug, and qualification

Requirements

What you’ll need

B.S./M.S. in Electrical Engineering or related field
Experience with multi-die package design and UCIe (AP/SP) integration
Understanding of substrate materials, stack-ups, and mechanical constraints
Familiarity with SI/PI concepts to collaborate effectively with electrical teams
Experience managing packaging subcontractors
Experience interfacing with TSMC/OSAT for bumping and packaging options
Knowledge of package modeling tools (HFSS, Sigrity, or similar) is a plus
Must be authorized to work in the United States

Benefits

Comp & perks

Meaningful equity
Benefits
401k