RTL Design Engineer

Delos Data

. Design and implement RTL for complex digital subsystems using Verilog/SystemVerilog .

Posted 10/20/2026full-timeRemote • California • United StatesMid-LevelSenior💰 $160,000 - $240,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in RTL design using Verilog/SystemVerilog, with a strong focus on microarchitecture principles and design correctness. Capable of collaborating across teams to ensure high-quality outcomes and continuous improvement in design methodologies.

Highest-signal resume keywords

RTL DesignVerilog/SystemVerilogMicroarchitecture PrinciplesSimulation and Debug ToolsAnalytical and Problem-Solving Skills

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

RTL DesignVerilogSystemVerilogMicroarchitectureSynchronous Digital DesignLintingCDC AnalysisSynthesis ReadinessTiming ClosureDesign Reviews

Soft Skills

Clear Communication SkillsAttention to DetailIndependent WorkTask Management

Tools & Technologies

VCSQuestaVerdiDVE

Industry Keywords

Electrical EngineeringComputer EngineeringDigital DesignDesign MethodologiesCross-Functional Collaboration

About the role

Key responsibilities & impact

Design and implement RTL for complex digital subsystems using Verilog/SystemVerilog
Translate architectural specifications into clean, efficient, and scalable microarchitectures
Collaborate with architecture, verification, and physical design teams to ensure design correctness and closure
Develop high-quality, reusable RTL with strong coding standards and documentation
Perform linting, CDC analysis, and ensure synthesis readiness of designs
Support integration and debug of RTL in simulation and early silicon environments
Participate in design reviews and provide technical input on architecture and implementation tradeoffs
Work with verification teams to ensure comprehensive functional coverage
Assist in timing closure and support backend teams as needed
Contribute to continuous improvement of design methodologies, flows, and tools

Requirements

What you’ll need

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
5+ years of experience in RTL design
Strong hands-on experience with Verilog/SystemVerilog
Solid understanding of synchronous digital design and microarchitecture principles
Experience with simulation and debug tools (e.g., VCS, Questa, Verdi, DVE)
Familiarity with synthesis, timing, and physical design constraints
Strong analytical and problem-solving skills
Clear written and verbal communication skills for cross-functional collaboration
High attention to detail and ability to deliver high-quality design outcomes
Ability to work independently and manage tasks to completion, including AI-assisted workflows
Authorized to work in the United States

Benefits

Comp & perks

Meaningful equity
Benefits
401(k)