SerDes Validation Engineer

Delos Data

. Own physical-layer implementation, configuration, tuning, and post-silicon validation of ultra-high-speed data links, including 112G and 224G PAM4 .

Posted 11/3/2026full-timePalo Alto • California • United StatesMid-LevelSenior💰 $180,000 - $260,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in physical-layer implementation and validation of ultra-high-speed data links, particularly 112G and 224G PAM4. Proficient in debugging and optimizing SerDes configurations while collaborating effectively with cross-functional teams.

Highest-signal resume keywords

Physical Layer ImplementationSerDes ConfigurationHigh-Speed Data Links ValidationAutomated Testing with PythonCollaboration with SI/PI Teams

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

PAM4 LinksSerDes ImplementationEqualization TuningDebuggingSignal IntegrityJitter Profile AnalysisBit Error Rate (BER) OptimizationChannel ModelingCompliance TestingProduction Validation

Soft Skills

Collaboration Skills

Tools & Technologies

BERTsOscilloscopesPattern GeneratorsProtocol AnalyzersScript-Based Automation

Industry Keywords

Data CenterNetworkingHigh-Performance ComputePCIe Gen5PCIe Gen6EthernetCXL

Tech Stack

Tools & technologies

Python

About the role

Key responsibilities & impact

Own physical-layer implementation, configuration, tuning, and post-silicon validation of ultra-high-speed data links, including 112G and 224G PAM4
Drive implementation and register-level configuration of high-speed SerDes IP blocks across custom hardware systems
Own transceiver equalization tuning, including CTLE, FFE, and DFE tap optimization, to maximize eye margin and minimize bit error rates across cable, backplane, and board-level topologies
Lead post-silicon physical-layer bring-up, characterization, and debugging of 112G and 224G PAM4 links
Use high-bandwidth oscilloscopes, BERTs, pattern generators, and protocol analyzers to validate link performance and isolate issues
Collaborate with SI/PI engineers to correlate lab-measured link behavior with layout, simulation, and channel models
Work with firmware teams to support real-time link monitoring, configuration control, and automated validation flows
Develop and run script-based lab automation, including Python-based test, measurement, and characterization workflows
Help define best practices for SerDes bring-up, tuning, debug, and validation across hardware platforms
Work closely with signal integrity, power integrity, hardware, firmware, and systems teams

Requirements

What you’ll need

Proven hands-on experience bringing up and validating physical 56G, 112G, or 224G PAM4 links, or high-speed PCIe Gen5/Gen6 interfaces
Deep practical understanding of SerDes implementation, configuration, equalization, and physical-layer debug
Strong knowledge of how TX/RX equalization settings affect signal integrity, jitter profiles, eye margin, and BER
Advanced proficiency with BERTs, real-time or sampling oscilloscopes, pattern generators, and protocol analyzers
Experience with automated, script-based testing and lab characterization, preferably using Python
Ability to debug complex link issues across silicon, board, cable, backplane, firmware, and system-level interactions
Strong collaboration skills and ability to work closely with SI/PI, hardware, firmware, and systems teams
Experience with 112G or 224G PAM4 links in data center, networking, switch, accelerator, or high-performance compute environments is nice to have
Familiarity with Ethernet, PCIe, CXL, or other high-speed protocols is nice to have
Experience with SerDes IP from major commercial IP providers or custom in-house SerDes teams is nice to have
Exposure to channel modeling, compliance testing, and production validation flows is nice to have
Authorization to work in the United States

Benefits

Comp & perks

Meaningful equity
Benefits
401(k)