Verification Engineer

Delos Data

. Develop, implement, and maintain RTL verification environments using UVM or equivalent methodologies .

Posted 10/16/2026full-timeRemote • United StatesSeniorLead💰 $160,000 - $240,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in RTL verification environments using UVM and SystemVerilog, with a strong focus on coverage-driven verification and automation using Python. Proven ability to analyze complex design issues and collaborate effectively with cross-functional teams to ensure high-quality verification outcomes.

Highest-signal resume keywords

RTL VerificationUVM MethodologiesSystemVerilog ProficiencyDigital Design VerificationEDA Tools Experience

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

RTL VerificationUVM MethodologiesSystemVerilogPython ScriptingCoverage-Driven VerificationFormal Verification TechniquesDigital Design FundamentalsHigh-Speed Communication ProtocolsTest Case DevelopmentRoot-Cause Analysis

Soft Skills

Analytical SkillsProblem-Solving SkillsClear CommunicationAttention to DetailIndependent Task Management

Tools & Technologies

Synopsys VCSSiemens/Mentor QuestaCadence Xcelium

Industry Keywords

Digital Design VerificationVerification ProcessesDesign TestabilityProcessor SubsystemsSoC-Level DesignsBus ProtocolsInterconnect Protocols

Tech Stack

Tools & technologies

Python

About the role

Key responsibilities & impact

Develop, implement, and maintain RTL verification environments using UVM or equivalent methodologies
Create and execute coverage-driven verification plans aligned with design specifications
Develop directed and constrained-random test cases and sequences to validate functionality and identify corner cases
Analyze simulation results, debug complex verification and design issues, and perform root-cause analysis in collaboration with RTL design engineers
Implement and track functional and code coverage, driving verification to closure
Develop reusable verification components and write SystemVerilog Assertions (SVA)
Participate in design and verification reviews, providing input on design testability, correctness, and optimization
Automate regression testing and enhance verification infrastructure using Python and scripting
Contribute to continuous improvement of verification processes, tools, and methodologies

Requirements

What you’ll need

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
7+ years of experience in digital design verification
Strong hands-on experience with UVM-based or similar verification methodologies
Proficiency in SystemVerilog, UVM, and Python
Experience with industry-standard EDA tools (e.g., Synopsys VCS, Siemens/Mentor Questa, Cadence Xcelium)
Solid understanding of digital design fundamentals
Experience verifying standard bus and interconnect protocols such as AXI, AXI-S, and APB
Experience with high-speed communication protocols including PCIe, Ethernet (10G/40G/100G), SPI, and I²C
Strong analytical and problem-solving skills
Clear written and verbal communication skills for cross-functional collaboration
High attention to detail and ability to deliver reliable, high-quality verification outcomes
Ability to work independently and manage tasks to completion
Experience with formal verification techniques and tools
Experience verifying processor subsystems or SoC-level designs
Authorization to work in the United States is addressed in the application form
Visa sponsorship requirements for work in the United States are addressed in the application form

Benefits

Comp & perks

Meaningful equity
Benefits
401(k)