Senior ASIC, Front End Design Engineer

Ethernovia

. Responsible for all aspects of digital SoC design, from micro-architecture specification, RTL, verification, synthesis, lint, CDC, LEC, and static timing analysis to delivering designs meeting target power, performance, and area goals .

Posted 9/28/2026full-timeToronto • CanadaSeniorWebsite

Core Competencies

Role fit

Core Competencies

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Expertise in digital SoC design, including RTL, verification, and synthesis, with a strong focus on delivering high-performance ASIC products. Proficient in collaborating with cross-functional teams to define specifications and integrate complex protocols and algorithms.

Highest-signal resume keywords

ASIC RTL DesignVerilog/System VerilogDigital Signal ProcessingNetworking ProtocolsCollaboration Skills

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Digital Design FundamentalsSoC DevelopmentStatic Timing AnalysisIP IntegrationDigital Mixed-Signal DesignPerlTCLC/C++MakeSimulation Tools

Soft Skills

Excellent CommunicationAttention to Detail

Certifications & Qualifications

BS in Electrical EngineeringMS in Computer Science

Industry Keywords

Automotive Communication SemiconductorsEthernet MACPHY/PCSTCP/IPPCIeVideo StandardsProcessing Algorithms

Tech Stack

Tools & technologies

PerlSwitchingTCP/IPC++

About the role

Key responsibilities & impact

Responsible for all aspects of digital SoC design, from micro-architecture specification, RTL, verification, synthesis, lint, CDC, LEC, and static timing analysis to delivering designs meeting target power, performance, and area goals
Work with system architects, software, hardware, and verification engineers to plan, architect, design, implement, and deliver advanced automotive communication semiconductors and systems
Develop and define advanced, high-performance custom silicon embodying functions from diverse protocols, algorithms, and applications
Define precise ASIC product specifications, including internal and external interactions, data flow, processing algorithms, resource management, and software interfaces
Work independently with little guidance or oversight

Requirements

What you’ll need

BS and/or MS in Electrical Engineering, Computer Science, or related field
Minimum 10+ years of ASIC RTL design and/or architecture experience
Proven track record with the development of complex SoCs
Strong understanding of digital design fundamentals and methodologies
In-depth knowledge of Verilog/System Verilog and simulation tools
Experience in networking, including Ethernet MAC, PHY/PCS, switching, TCP/IP, PCIe and other industry standard protocols
Experience with digital signal processing filters
Experience with digital mixed-signal modeling, design, and integration
Experience with IP integration, including SerDes, controllers, and processors
Experience with video standards, protocols, and processing
Experience with Perl, TCL, C/C++, and Make
Excellent communication/documentation skills
Attention to details
Collaboration across multidisciplinary and international teams

Benefits

Comp & perks

Pre IPO stock options
Competitive base salary
Flexible hours
Medical, dental and vision insurance for employees
Technology depth and breadth expansion that can’t be found in a large company
Opportunity to grow your career as the company grows
Cutting edge technology
World class team