Verification Designer

Fidus Systems

. Own block- and system-level verification of ASIC and FPGA designs from test plan development through coverage closure .

Posted 9/19/2026full-timeRemote • Arizona • United StatesSeniorLeadWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates extensive experience in ASIC and FPGA verification, with a strong command of SystemVerilog and UVM methodologies. Proficient in developing verification environments and automating tasks using Python, Perl, or Tcl, while effectively collaborating with cross-functional teams and clients.

Highest-signal resume keywords

ASIC/FPGA Verification ExperienceSystemVerilog ProficiencyUVM Methodology FluencyConstrained-Random Verification ExperienceDebugging and Problem-Solving Skills

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

ASIC VerificationFPGA VerificationSystemVerilogUVMConstrained-Random VerificationFunctional CoverageAssertionsFormal VerificationPythonPerl

Soft Skills

Interpersonal SkillsTeamworkCommunication SkillsClient-Facing ComfortAnalytical Skills

Tools & Technologies

CocoTBPyUVMDPI-CSimulation ToolsRegression Monitoring

Certifications & Qualifications

Bachelor's Degree in Electrical EngineeringMaster's Degree in Computer Engineering

Industry Keywords

Verification LeadCoverage MetricsDebuggingAI in EngineeringEmbedded SoftwareNetworkingARM CPU SubsystemsElectronic SystemsMedical ApplicationsAutomotive Applications

Tech Stack

Tools & technologies

PerlPython

About the role

Key responsibilities & impact

Own block- and system-level verification of ASIC and FPGA designs from test plan development through coverage closure
Design and implement UVM, formal, and assertion-based verification environments using constrained-random verification techniques
Develop behavioral models and test cases to achieve functional coverage goals
Define and track coverage metrics through closure
Debug and troubleshoot simulation and regression failures
Collaborate with designers and system architects to resolve issues
Automate verification tasks and monitor regressions using Python, Perl, or Tcl
Plan, execute, and report status on multiple verification activities as verification lead
Work directly with external clients on verification strategy and support
Collaborate across FPGA/DSP, hardware, embedded software, verification, SI/PI, PCB layout, and mechanical/thermal design teams
Deliver electronic systems for clients across space, communications, compute, storage, video, imaging, VR/AR, industrial, medical, and automotive applications

Requirements

What you’ll need

8+ years of ASIC/FPGA verification experience, with proven verification-lead ownership
Strong SystemVerilog and UVM methodology fluency
Constrained-random verification (CRV) experience
Experience with functional coverage, assertions, and formal verification techniques
Familiarity with Ethernet, DDR/LPDDR, HBM, security, networking, AXI, NoC, and ARM CPU subsystems
Experience with cocoTB, pyUVM, or DPI-C is a plus
Proficiency in Python, Perl, or Tcl
Strong debugging, problem-solving, and analytical skills
Strong interpersonal, teamwork, and communication skills; comfortable being client-facing
Embraces AI as part of a modern engineering toolkit
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field
May be required to travel domestically and internationally

Benefits

Comp & perks

Medical, dental, and vision plans
Matching 401(k) contributions
Annual profit-sharing bonus
Other supplementary benefits
Fully remote work arrangement
Domestic and international travel support for customer engagements and project delivery