Principal FPGA Networking Engineer

GE Aerospace

. Architect, implement, and verify FPGA-based networking solutions for space-based electronic systems .

Posted 9/18/2026full-timeRemote • United StatesLead💰 $91,000 - $216,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

Use this summary to align your resume positioning with the role.

Demonstrates expertise in FPGA-based networking design, including VHDL coding, Ethernet protocols, and high-speed serial interfaces. Proficient in simulation, verification, and integration of complex networking solutions within electronic systems.

Highest-signal resume keywords

FPGA-Based Networking DesignVHDL CodingEthernet ProtocolsSimulation TestbenchesHigh-Speed Serial Interfaces

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

FPGA Design MethodologyRTL Logic DesignPacket-Switched ArchitecturesTiming Closure TechniquesFirmware/RTL DesignNetworking Protocols ImplementationData Networking ArchitecturesPerformance EvaluationProtocol Compliance TestingC/C++ Programming

Soft Skills

Mentoring Junior EngineersCollaboration with EngineersIndependent Contribution

Tools & Technologies

Vivado Design SuiteVivado IP IntegratorModelSimQuestaSimAldec Simulation ToolsLinuxGit

Industry Keywords

Ethernet MAC/PHY IntegrationQoSIPsecMACsecHigh-Speed Ethernet InterfacesMulti-Level Security NetworkingBuffering and Queuing SchemesTraffic GenerationFPGA ILA-Based DebuggingElectronic Lab Equipment

Tech Stack

Tools & technologies

LinuxSwitchingC++

About the role

Key responsibilities & impact

Architect, implement, and verify FPGA-based networking solutions for space-based electronic systems
Design on-board networking, data transport, RF, processing, and data storage solutions using AMD (Xilinx) technologies
Architect networking pipelines covering Ethernet MAC/PHY integration, packet parsing/classification, switching/forwarding, buffering, and QoS
Design packet-switching fabrics, router/switch datapaths, control logic, and buffering/queuing schemes
Create and maintain FPGA designs using VHDL and Vivado IP Integrator
Code, simulate, and verify Ethernet interfaces, packet-processing blocks, switching/routing/queuing logic, and control interfaces
Implement solutions using embedded ARM processors, DDR4 memory, and high-speed serial interfaces such as Aurora, PCIe, and multi-rate Ethernet
Implement and optimize hardware support for IP, TCP/UDP, VLAN, and QoS, including offload engines and checksum/segmentation logic
Develop and maintain simulation testbenches
Define timing constraints and perform timing closure for multi-clock, multi-interface designs
Produce design documentation, interface control documents, and performance characterization reports
Participate in code and design reviews and contribute to FPGA design methodologies
Collaborate with hardware and software engineers to integrate FPGA networking designs with system hardware, drivers, and networking stacks
Support board bring-up and system verification, including link bring-up, traffic generation, protocol compliance testing, performance evaluation, and FPGA ILA-based debugging
Mentor junior engineers in FPGA networking architecture, protocol implementation, buffering/queuing, and verification practices

Requirements

What you’ll need

Bachelor’s degree in Computer Engineering, Electrical Engineering, or related technical degree
9+ years of related experience with a bachelor’s degree OR 7+ years of experience with a master’s degree
Hands-on experience with FPGA-based networking design, including Ethernet (IEEE 802.3), high-speed serial links, and packet-switched architectures
Experience implementing or integrating networking protocols and functions in hardware, including IP, TCP/UDP, VLAN, QoS, router/switch datapaths, and routing look-up tables
Experience with firmware/RTL design, simulation, and verification for complex, high-throughput FPGA systems
Experience with RTL logic design and coding using VHDL and/or Verilog
Thorough understanding of FPGA design methodology, including physical synthesis, static timing analysis, place/route, verification, power analysis, and timing closure techniques
Experience writing simulation testbenches
Preferred: deep understanding of data networking architectures, routers, switches, and network management concepts
Preferred: experience with high-speed Ethernet interfaces, including 100G Ethernet
Preferred: experience with multi-level security networking concepts and architectures
Preferred: experience with IPsec and MACsec
Preferred: experience designing and verifying hardware buffering and queuing schemes, including FIFOs, circular buffers, and priority queues
Preferred: experience with networking test and qualification, including performance and protocol compliance testing
Preferred: experience with AMD (Xilinx) SoC/FPGA devices and Vivado Design Suite
Preferred: experience with Vivado IP Integrator
Preferred: experience with Microsemi (Microchip) FPGAs and Libero
Preferred: experience with ModelSim/QuestaSim and/or Aldec simulation tools
Preferred: experience with UVVM, UVM, OVM, or similar simulation verification libraries
Preferred: experience with board bring-up, electronic lab equipment, and FPGA ILA-based debugging tools
Preferred: experience with revision control systems such as Git
Experience with Linux
Experience with C/C++
Ability to contribute independently and within a distributed team

Benefits

Comp & perks

Health benefits
Medical
Dental
Vision
Basic life with AD&D
Short term disability
Long term disability
Ancillary benefits: voluntary life with AD&D, accident, critical illness, hospital, and pet
Spending accounts: HSA, FSA, and DCFSA
Paid time off
Holidays
401(k), including company match
Tuition reimbursement
Parental, maternity, and military leaves
Annual discretionary bonus for eligible roles