FPGA Engineer

GROUPE LR TECHNOLOGIES

. Design and develop FPGA functions in VHDL or Verilog for H.264 (AVC) and H.265 (HEVC) video compression pipelines .

Posted 9/24/2026full-timeLes Ulis • FranceJuniorMid-Level💰 €40,000 - €45,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in FPGA development using VHDL or Verilog, with a strong focus on video compression technologies such as H.264 and H.265. Proficient in simulation and debugging, with a solid understanding of hardware design and validation processes.

Highest-signal resume keywords

FPGA DevelopmentVHDLVivadoH.264/H.265 Video CompressionSimulation and Debugging

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

FPGA DevelopmentVHDLVerilogH.264H.265SimulationTiming ClosureSynthesisPlace-and-RouteAXI Buses

Soft Skills

Self-MotivatedAttention to DetailTeam-OrientedExcellent Documentation SkillsAutonomous Learning

Tools & Technologies

VivadoQuartusModelSimQuesta

Certifications & Qualifications

Master's Degree in ElectronicsSecret Défense Security Clearance

Industry Keywords

Video CompressionAerospaceSpaceDefenseDigital Electronics

About the role

Key responsibilities & impact

Design and develop FPGA functions in VHDL or Verilog for H.264 (AVC) and H.265 (HEVC) video compression pipelines
Integrate and configure video encoding IP cores and associated interfaces
Write testbenches and perform simulations using ModelSim/Questa
Perform synthesis, place-and-route, and timing closure using Vivado or Quartus
Debug and validate designs on hardware boards in collaboration with hardware and systems teams
Maintain and enhance existing designs, including bug fixes, functional updates, and obsolescence management
Produce design and validation documentation
Contribute to a video acquisition and compression system for a major aerospace, space, and defense customer

Requirements

What you’ll need

Master's degree (engineering degree or equivalent) in electronics, digital electronics, microelectronics, or embedded systems
2–5 years of hands-on experience in FPGA development
Proficiency in VHDL (or Verilog/SystemVerilog) and the Vivado or Quartus toolchain
Knowledge of video compression principles: H.264/H.265, GOP, macroblocks/CTUs, bitrate/quality trade-offs
Solid experience with simulation, AXI buses, and hardware debugging
Self-motivated and autonomous, with the ability to learn quickly, strong attention to detail, excellent documentation skills, and a team-oriented mindset
French nationality required due to Secret Défense security clearance requirements

Benefits

Comp & perks

Permanent employment contract with close support: a manager and a recruitment specialist who support your career beyond the assignment
Technically challenging, high-value projects in the aerospace, space, and defense sectors
Great Place to Work-certified and ECOVADIS-labeled company
Career development opportunities: technical expertise, subject-matter expert roles, project leadership, and mobility between business units