FPGA Engineer – High-Speed Digital Design

Helvetic Payroll

. Support FPGA prototyping for high-speed digital designs related to PHY and SerDes IP .

Posted 10/8/2026contractLausanne • SwitzerlandSeniorLeadWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates extensive experience in FPGA design and prototyping, with strong RTL coding skills in SystemVerilog and proficiency in high-speed digital design validation. Capable of collaborating effectively with cross-functional teams to enhance development and validation environments.

Highest-signal resume keywords

FPGA DesignSystemVerilog CodingHigh-Speed Digital DesignDesign ValidationUVM Methodologies

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

FPGA PrototypingRTL CodingDesign ValidationHigh-Speed InterfacesDigital DesignVerificationTroubleshootingSimulationScripting (Python)Multi-Gigabit Transceivers

Soft Skills

Analytical SkillsCommunication SkillsTeamwork Skills

Tools & Technologies

FPGA ToolsVerification ToolsDevelopment Environments

Industry Keywords

PHYSerDes IPDigital BlocksPCSVerification Methodologies

Tech Stack

Tools & technologies

Python

About the role

Key responsibilities & impact

Support FPGA prototyping for high-speed digital designs related to PHY and SerDes IP
Contribute to validation and bring-up of devices and FPGAs in the laboratory
Work closely with Firmware, Digital Design, Verification, and Lab teams
Support design validation, testing, and troubleshooting activities
Contribute to setup and improvement of development and validation environments

Requirements

What you’ll need

At least 10 years of experience in FPGA design and prototyping
Strong experience designing and prototyping FPGA blocks for multi-Gigabit serial and parallel data-link transceivers
Excellent RTL coding skills, preferably in SystemVerilog
Experience with industry-standard FPGA tools for design, simulation, and verification
Experience with Python or another scripting language for design validation and tool setup
Strong technical background in FPGA design, validation, and verification
Experience with high-speed digital blocks
Knowledge of high-speed interfaces and/or PCS is an advantage
Good understanding of verification methodologies
Experience with UVM is a plus
Strong analytical, communication, and teamwork skills

Benefits

Comp & perks

Flexible employment solutions
Remote work after the initial hybrid period
Hybrid work model with three days per week on-site and two days remote during the first two weeks
Option to remain hybrid throughout the three-month assignment