Senior/Staff Physical Verification, PDK Engineer

HyperLight

. Own physical verification for the TFLN-on-silicon-photonics stack, including deck architecture, partitioning, hierarchy and runtime, results triage, and waiver workflow .

Posted 9/22/2026full-timeCambridge • Massachusetts • United StatesSenior💰 $150,000 - $225,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in physical verification processes, including DRC and LVS signoff, while managing PDK development and integration across multiple material platforms. Effectively communicates with foundry and customer teams to guide technical decisions and support active tapeouts.

Highest-signal resume keywords

Physical Verification ExpertiseDRC and LVS SignoffPDK Development and SupportTechnical Communication SkillsAdvanced-Node Foundry Flows

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Physical VerificationDRC Rule Deck AuthoringLVS Rule Deck AuthoringPDK IntegrationModel IntegrationDebuggingScripting (SKILL)Multi-Die Verification3D Integrated Products VerificationDesign Rule Checks

Soft Skills

Professional CommunicationTechnical LeadershipDecision-Making Under Pressure

Tools & Technologies

Synopsys IC ValidatorSiemens CalibreCadence VirtuosoPegasus

Industry Keywords

Electrical EngineeringComputer EngineeringPhysicsFoundry InterfaceAdvanced PackagingTapeout Support

Tech Stack

Tools & technologies

AssemblyNode.js

About the role

Key responsibilities & impact

Own physical verification for the TFLN-on-silicon-photonics stack, including deck architecture, partitioning, hierarchy and runtime, results triage, and waiver workflow
Stand up and run DRC and LVS signoff using tools such as Synopsys IC Validator and Siemens Calibre
Lead internal and cross-platform design rule checks for the platform
Own the heterogeneous PDK end to end, including architecture, model integration, release and qualification criteria, documentation, and support
Serve as the primary technical interface to foundry and customer verification teams on rule interpretation, waivers, and deck issues
Support active tapeouts
Serve as a technical expert guiding engineering decisions and the technical roadmap
Manage design tradeoffs and enablement across multiple material platforms
Build physical verification and design enablement work into a full PDK

Requirements

What you’ll need

Either 6+ years of relevant work experience or equivalent experience through an advanced degree (M.S. or Ph.D.) in Electrical Engineering, Computer Engineering, Physics, or a related field
Hands-on experience authoring and debugging production DRC and LVS rule decks in IC Validator, Calibre, or Pegasus — not only running decks written by others
Familiarity with Cadence Virtuoso or comparable commercial layout and PDK environments, including techfiles, PCells, compact models, and scripting (e.g., SKILL)
Demonstrated ability to communicate professionally and effectively with foundry and customer engineering teams, including holding a technical position under pressure
Experience developing, releasing, and supporting PDKs used by external customers (preferred)
Experience with physical verification of multi-die, 2.5D, or 3D integrated products, including interface and assembly-level checks (preferred)
Experience with advanced-node or advanced-packaging foundry flows and design enablement (preferred)
Experience hiring and/or growing engineers and owning a broad technical scope (preferred)
Authorization to work in the US

Benefits

Comp & perks

Comprehensive health coverage, including medical, vision, and dental plans for individuals and families
401(k) retirement plans with employee matching
Paid parental leave
Life and disability insurance
Commuter benefits and subsidies
Professional growth and mentorship opportunities
Periodic travel to the Cambridge, MA office
Remote work from within the US
Onsite work option for candidates local to the Boston area